Arm Cortex R4F User Manual download pdf (Page 64)

Programmer’s Model

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Because SVC handlers are always expected to return after the

SVC

instruction, the IT

execution state bits are automatically advanced when an exception is taken prior to

copying the CPSR into the SPSR.

2.8.2 Reset

When the nRESET signal is driven LOW a reset occurs, and the processor abandons the

executing instruction.

When nRESET is driven HIGH again the processor:

1. Forces CPSR M[4:0] to b10011 (Supervisor mode) and sets the A, I, and F bits in the

CPSR. The E bit is set based on the state of the CFGEE pin. Other bits in the CPSR are

indeterminate.

2. Forces the PC to fetch the next instruction from the reset vector address.

3. Reverts to ARM state or Thumb state depending on the state of the TEINIT pin, and

resumes execution.

After reset, all register values except the PC and CPSR are indeterminate.

See Chapter 3 Processor Initialization, Resets, and Clocking for more information on the reset

behavior for the processor.

2.8.3 Interrupts

The processor has two interrupt inputs, for normal interrupts (nIRQ) and fast interrupts (nFIQ).

Each interrupt pin, when asserted and not masked, causes the processor to take the appropriate

type of interrupt exception. See Exceptions on page 2-16 for more information. The CPSR.F and

CPSR.I bits control masking of fast and normal interrupts respectively.

A number of features exist to improve the interrupt latency, that is, the time taken between the

assertion of the interrupt input and the execution of the interrupt handler. By default, the

processor uses the Low Interrupt Latency (LIL) behaviors introduced in version 6 and later of

the ARM Architecture. The processor also has a port for connection of a Vectored Interrupt

Controller (VIC), and supports Non-Maskable Fast Interrupts (NMFI).

The following subsections describe interrupts:

• Interrupt request

• Fast interrupt request on page 2-19

• Non-maskable fast interrupts on page 2-19

• Low interrupt latency on page 2-19

• Interrupt controller on page 2-20.

Interrupt request

The IRQ exception is a normal interrupt caused by a LOW level on the nIRQ input. An IRQ

has a lower priority than an FIQ, and is masked on entry to an FIQ sequence. You must ensure

that the nIRQ input is held LOW until the processor acknowledges the interrupt request, either

from the VIC interface or the software handler.

Irrespective of whether the exception is taken from ARM state or Thumb state, an IRQ handler

returns from the interrupt by executing:

SUBS PC, R14_irq, #4

1 2 ... 59 60 61 62 63 64 65 66 67 68 69 ... 455 456

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