ARM AMBA NIC-301 Specifications download pdf (Page 93)

Programmers Model

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Test chip SCC Register 42

The CFGREG42 Register characteristics are:

Purpose Cortex-A15 configuration register 1 that enables you to read and write

Cortex-A15 cluster configuration settings.

Usage constraints There are no usage constraints.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-20 on page 3-37 shows the bit assignments.

[19:18] - Reserved. Do not modify.

[17:16] DBGEN[1:0] Maps to the DBGEN invasive debug enable bus for both Cortex-A15 cores:

Disable invasive debug.

Enable invasive debug.

The default is

b11

[15:14] - Reserved. Do not modify.

[13:12] CFGTE[1:0] Maps to the Thumb Exception Enable bus for both Cortex-A15 cores:

Exception, including reset, taken in ARM state.

Exception, including reset, taken in Thumb state.

The default is

b00

[11:10] - Reserved. Do not modify.

[9:8] VINITHI_CORE[1:0] Location of the exception vectors at reset for both Cortex-A15 cores:

Exception vectors start at address

0x0000_0000

Exception vectors start at address

0xFFFF_0000

The default is

b00

[7] IMINLN Instruction cache minimum line size:

32 bytes.

64 bytes.

The default is

[6:4] - Reserved. Do not modify.

[3:0] CLUSTER_ID A15 cluster ID. The default is

b0000

Table 3-21 Test chip CFGREG41 Register bit assignments (continued)

Bits Name Function

1 2 ... 88 89 90 91 92 93 94 95 96 97 98 ... 177 178

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ARM AMBA NIC-301 Specifications Page 93