ARM VERSION 1.2 Datasheet Page 145

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Semihosting
ARM DUI0058D Copyright © 1999-2001 ARM Limited. All rights reserved. 5-7
Multi-ICE handles the semihosted SWI and then examines the contents
of lr and returns to the instruction following the SWI instruction in your
code.
Regardless of the value of
$vector_catch
, all exceptions and interrupts are
trapped and reported as an error condition.
For details of how to modify debugger internal variables, see the appropriate debugger
documentation.
5.2.5 Multi-ICE DCC semihosting
Multi-ICE can also use the debug communications channel so that the core is not
stopped while semihosting takes place. This is enabled by setting
$semihosting_enabled
to 2. Refer to the Multi-ICE User Guide for more details.
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