ARM Cortex R4 Specifications download pdf (Page 4)

Standard Initialization Sequence for Hercules Microcontrollers

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27. Start a self-test on all on-chip dual-port SRAMs using the PBIST controller (Section 2.22).

28. Run the self-test on the CPU's SECDED logic for accesses to main data RAM (B0TCM and B1TCM)

(Section 2.23).

29. Run the self-test on the CPU's SECDED logic for accesses to the main Flash memory (ATCM)

(Section 2.24).

30. Wait for self-test to complete and pass on all on-chip dual-port SRAMs.

31. Start a self-test on all on-chip single-port SRAMs excluding the CPU RAM using the PBIST controller

(Section 2.25).

32. Wait for self-test to complete and pass on all on-chip single-port SRAMs.

33. Start auto-initialization for all other on-chip SRAMs (Section 2.26).

34. Check if the auto-initialization process for all RAMs is completed; wait here if it has not completed.

35. Check the parity error detection mechanism for all peripheral memories (Section 2.27).

36. Enable the CPU’s dedicated vectored interrupt controller (VIC) port (Section 2.28).

37. Program all interrupt service routine addresses in the vectored interrupt manager (VIM) memory

(Section 2.29).

38. Configure IRQ and FIQ interrupt priorities for all interrupt channels (Section 2.29.1).

39. Enable the desired interrupts (IRQ or FIQ) inside the CPU (Section 2.30).

40. Enable the desired interrupts in the VIM control registers (Section 2.29.2).

41. Set up the application responses to inputs to the error signaling module (ESM) (Section 2.31).

42. Initialize copy table, global variables, and constructors (Section 2.32).

43. Verify that the dual-clock-comparator (DCC) module can actually detect and flag a frequency error

(Section 2.33).

44. Configure the DCC module to continuously monitor the PLL output(Section 2.33).

45. Verify that a memory protection unit (MPU) violation for all bus masters is flagged as an error to the

ESM(Section 2.33).

46. Run a background check on entire Flash using CRC(Section 2.33).

47. Run the offset error calibration routine for the analog-to-digital converter (ADC)(Section 2.33).

48. Run a self-test on the ADC analog input channels(Section 2.33).

49. Check I/O loop-back for all peripherals(Section 2.33).

50. Set up the MPU for the bus masters(Section 2.33).

51. Set up the digital windowed watchdog (DWWD) module service window size and the module response

on a violation (reset or NMI)(Section 2.33).

52. Configure desired access permissions for peripherals using the peripheral central resource (PCR)

controller registers(Section 2.33).

53. Configure the external safety companion (for example, TI TPS6538x, for online diagnostic

operation)(Section 2.33).

54. Set up the real-time interrupt (RTI) module for generating periodic interrupts as required by the

application(Section 2.33).

55. Call the main application (Section 2.34).

2.1 Initialize Cortex™-R4 Registers

The TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontrollers include dual Cortex-R4

CPUs running in a lock-step operation mode. A core compare module (CCM-R4) compares the output

signals from each R4 CPU. Any difference in the two CPUs’ outputs is flagged as a fault of a high-severity

level. The CPU internal registers are not guaranteed to power up in the same state for both the CPUs.

The CPU pushes the internal registers on to the stack on a function call, which could lead to the detection

of a core compare error. Therefore, the CPU internal core registers need to be initialized to a predefined

state before any function call is made.

Initialization of the TMS570LS043x, TMS570LS033x and RM42L432 SPNA163–September 2012

Hercules ARM Cortex-R4 Microcontrollers

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