ARM ARM1176JZF-S User Manual

1Confidential11ARM Architecture Overview222Development of the ARM Architecture4TARM7TDMIARM922TThumb instruction setARM926EJ-SARM946E-SARM966E-SImprov

10Confidential191919ARM1176JZ(F)-S Processor Core§TrustZone§8-stage pipeline§Branch prediction§Four AXI memory ports§IEM (Intelligent Energy Managemen

11Confidential212121ARM Cortex-M3 Processor§Architecture v7-M (Thumb-2 only) àVery different from previous ARM processors§ No CPSR register§ Vector ta

12Confidential232323The Instruction Pipeline242424The Instruction Pipeline§The ARM7TDMI uses a 3-stage pipeline in order to increase the speed of the

13Confidential252525CycleOperationADDSUBORRANDEORORROptimal Pipelining§All operations here are on registers (single cycle execution)§In this example i

14Confidential272727Cortex-A8 Integer PipelineInstruction Execute / Load StoreInstruction FetchF1 F2F0Instruction DecodeReplay PenaltyD0 D1

15Confidential292929Reference Material§ARM ARM(“Architecture Reference Manual”)§ ARM DDI 0100E covers v5TE DSP extensions§ Can be purchased from book

16Confidential313131Which architecture is my processor?Processor core Architecture§ARM7TDMI family v4T§ARM720T, ARM740T§ARM9TDMI family v4T§ARM920T,AR

17Confidential333333ARMv5 Cores:YesYesYesMMU or MPU8 WordsData or AddressWrite ThroughWrite BackRandomRound Robin0-1024K Instr0-1024K Data4-way0-128K

18Confidential353535Cortex Cores:AXIAXIAHB Lite/APBAHB Lite/APBBusYesYesYesYesStandby ModeYes YesNo No VFP SupportYesYesMPU (optional)Write ThroughWri

19Confidential373737NEON Media Processor Features§Single Instruction Multiple Data (SIMD) Media Processor§Targets audio and video codecs, image and sp

2Confidential333ARM Architecture profiles§Application profile (ARMv7-A à e.g. Cortex-A8)§Memory management support (MMU)§Highest performance at low po

3Confidential555Data Sizes and Instruction Sets§When used in relation to the ARM:§Halfword means 16 bits (two bytes)§Word means 32 bits (four bytes)§D

4Confidential777The ARM Register Setr0r1r2r3r4r5r6r7r8r9r10r11r12r15 (pc)cpsrr13 (sp)r14 (lr)User modespsrr13 (sp)r14 (lr)IRQ FIQr8r9r10r11r12r13 (sp)

5Confidential999Data alignment§Prior to architecture v6 data accesses must be appropriately aligned for access size§Unaligned addresses will produce u

6Confidential111111Introduction toInstruction Sets121212ARM Instruction Set§All instructions are 32 bits long / many execute in a single cycle§Instruc

7Confidential131313Thumb Instruction Set§Thumb is a 16-bit instruction set§Optimized for code density from C code (~65% of ARM code size)§Improved per

8Confidential151515Thumb 2 Performance / DensityPerformanceCode density100% ARM code100% Thumb codeRandom mix ‘Profiled’ mixThumb-2161616Processor Cor

9Confidential171717ARM7TDMI Processor§Architecture v4T§3-stage pipeline§Single interface to memory181818ARM926EJ-S ProcessorARM926EJ-S§Architecture v5