ARM ARM7TDMI User Manual

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0234BARM7TDMI-SRevision: r4p3Technical Reference Manual

List of Figuresx Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFigure 5-1 Typical debug system ...

Coprocessor Interface 4-12 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BThe fragments of Verilog that describe the register logic t

Coprocessor Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 4-134.5.2 Connecting multiple coprocessorsIf you have multiple

Coprocessor Interface 4-14 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B4.6 Not using an external coprocessor If you are implementi

Coprocessor Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 4-154.7 Undefined instructionsThe ARM7TDMI-S processor implemen

Coprocessor Interface 4-16 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B4.8 Privileged instructionsThe output signal CPnTRANS enabl

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-1Chapter 5 Debugging Your SystemThis chapter describes the debug features of the AR

Debugging Your System 5-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B• Watchpoint unit registers on page 5-48• Programming breakp

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-35.1 About debugging your systemThe advanced debugging featur

Debugging Your System 5-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BDebug target The ARM7TDMI-S processor has hardware extensio

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-55.2 Controlling debuggingThe major blocks of the ARM7TDMI-S

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. xiPrefaceThis preface introduces the ARM7TDMI-S processor and its reference documenta

Debugging Your System 5-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFor more information, see Entry into debug state on page 5-7

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-75.3 Entry into debug stateIf the system is in halt mode, any

Debugging Your System 5-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFigure 5-3 Debug state entry5.3.1 Entry into debug state on

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-95.3.2 Entry into debug state on watchpointWatchpoints occur

Debugging Your System 5-10 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BCaution Do not reset the core while debugging, otherwise th

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-11Figure 5-4 Clock synchronizationNote All the D-types shown

Debugging Your System 5-12 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.4 Debug interfaceThe ARM7TDMI-S processor debug interface

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-135.5 ARM7TDMI-S core clock domainsThe ARM7TDMI-S processor h

Debugging Your System 5-14 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.6 The EmbeddedICE-RT macrocellThe ARM7TDMI-S processor Em

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-15The EmbeddedICE-RT logic comprises the following:Two real-t

Preface xii Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BAbout this documentThis document is a reference manual for the ARM7TDMI-S

Debugging Your System 5-16 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.7 Disabling EmbeddedICE-RTYou can disable EmbeddedICE-RT

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-175.8 EmbeddedICE-RT register mapThe locations of the Embedde

Debugging Your System 5-18 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.9 Monitor mode debuggingThe ARM7TDMI-S (Rev 4) processor

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-19The monitor mode enable bit does not put the ARM7TDMI-S pro

Debugging Your System 5-20 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.10 The debug communications channelThe ARM7TDMI-S (Rev 4)

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-21The DCC control register bit assignments are shown in Table

Debugging Your System 5-22 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BMRC CP14, 0, Rd, C1, C0 Returns the value from the DCC data

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-23• If the R bit is set, previously deposited data has not ye

Debugging Your System 5-24 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.11 Scan chains and the JTAG interfaceThere are two JTAG-s

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-25Scan chain 2Scan chain 2 enables access to the EmbeddedICE-

Preface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. xiiiAppendix A Signal Descriptions Read this chapter for a list of all ARM7TD

Debugging Your System 5-26 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.12 The TAP controllerThe TAP controller is a state machin

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-275.12.1 Resetting the TAP controllerTo force the TAP control

Debugging Your System 5-28 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.13 Public JTAG instructionsTable 5-3 shows the public JTA

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-29• When the INTEST instruction is loaded into the instructio

Debugging Your System 5-30 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B• The bypass register is not affected in the UPDATE-DR stat

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-315.14 Test data registersThe six test data registers that ca

Debugging Your System 5-32 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BThe default device identification code is 0x7f1f0f0f.Operat

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-33The currently-selected scan chain changes only when a SCAN_

Debugging Your System 5-34 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BAll the control signals for the scan cells are generated in

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-35During UPDATE-DR, this register is either read or written d

Preface xiv Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BKey to timing diagram conventionsShaded bus and signal areas are undefined

Debugging Your System 5-36 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.15 Scan timingFigure 5-10 provides general scan timing in

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-378 DATA[7] Input/output9 DATA[8] Input/output10 DATA[9] Inpu

Debugging Your System 5-38 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B31 DATA[30] Input/output32 DATA[31] Input/output33 DBGBREAK

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-395.16 Examining the core and the system in debug stateWhen t

Debugging Your System 5-40 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BNote The use of r0 as the base register for the STM is only

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-41An instruction placed in scan chain 1 with bit 33, the DBGB

Debugging Your System 5-42 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.17 Exit from debug stateLeaving debug state involves:• re

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-43Figure 5-11 Debug exit sequenceFigure 5-3 on page 5-8 shows

Debugging Your System 5-44 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.18 The program counter during debugThe debugger must keep

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-455.18.3 Watchpoint with another exceptionIf a watchpointed a

Preface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. xvOther publicationsThis section lists relevant documents published by third

Debugging Your System 5-46 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.18.5 System speed accessWhen a system speed access is per

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-475.19 Priorities and exceptionsWhen a breakpoint, or a debug

Debugging Your System 5-48 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.20 Watchpoint unit registersThe two watchpoint units, kno

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-49Figure 5-12 EmbeddedICE-RT block diagramThe data to be writ

Debugging Your System 5-50 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BA register is read by shifting its address into the address

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-51The bits have the following functions:WRITE Compares agai

Debugging Your System 5-52 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BThe CHAINOUT register is cleared when the control value reg

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-535.21 Programming breakpointsBreakpoints are classified as h

Debugging Your System 5-54 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.21.2 Software breakpointsTo make a watchpoint unit cause

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-555.22 Programming watchpointsTo make a watchpoint unit cause

Preface xvi Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFeedbackARM Limited welcomes feedback both on the ARM7TDMI-S processor, an

Debugging Your System 5-56 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.23 Abort status registerOnly bit 0 of this 32 bit read/wr

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-575.24 Debug control registerThe debug control register is si

Debugging Your System 5-58 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.24.1 Disabling interruptsIRQs and FIQs are disabled under

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-595.24.3 Forcing DBGACKFigure 5-17 on page 5-61 shows that th

Debugging Your System 5-60 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.25 Debug status registerThe debug status register is 5 bi

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-61Figure 5-17 Debug control and status register structureBit

Debugging Your System 5-62 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B5.26 Coupling breakpoints and watchpointsYou can couple wat

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-63breakpoint chained together. The watchpoint address points

Debugging Your System 5-64 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BIf Watchpoint 0 matches but Watchpoint 1 does not (that is

Debugging Your System ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 5-655.27 EmbeddedICE-RT timingEmbeddedICE-RT samples the DBGEXT

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-1Chapter 1 IntroductionThis chapter introduces the ARM7TDMI-S processor. It contain

Debugging Your System 5-66 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 6-1Chapter 6 ETM InterfaceThis chapter describes the ETM interface that is provided o

ETM Interface 6-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B6.1 About the ETM interfaceYou can connect an external Embedded Trac

ETM Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 6-36.2 Enabling and disabling the ETM7 interfaceUnder the control of th

ETM Interface 6-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B6.3 ETM7 to ARM7TDMI-S (Rev 4) connectionsThe ETM7 interface port na

ETM Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 6-5RANGEOUT[0] DBGRNG[0]RANGEOUT[1] DBGRNG[1]RDATA[31:0] RDATA[31:0]TBI

ETM Interface 6-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B6.4 Clocks and resetsThe ARM7TDMI-S (Rev 4) processor uses a single

ETM Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 6-76.5 Debug request wiringIt is recommended that you connect together

ETM Interface 6-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-1Chapter 7 Instruction Cycle TimingsThis chapter gives the ARM7TDMI-S processor ins

Introduction 1-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B1.1 About the ARM7TDMI-S processorThe ARM7TDMI-S processor is a membe

Instruction Cycle Timings 7-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B• Coprocessor register transfer (move from coprocessor t

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-37.1 About the instruction cycle timingsThe TRANS[1:0] si

Instruction Cycle Timings 7-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BNote All cycle counts in this chapter assume zero-wait-s

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-57.2 Instruction cycle count summaryIn the pipelined arch

Instruction Cycle Timings 7-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BThe cycle types N, S, I, and C are defined in Table 7-1

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-77.3 Branch and ARM branch with linkAny ARM or Thumb bran

Instruction Cycle Timings 7-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B7.4 Thumb branch with linkA Thumb Branch with Link (BL)

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-97.5 Branch and exchangeA Branch and eXchange (BX) operat

Instruction Cycle Timings 7-10 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B7.6 Data operationsA data operation executes in a singl

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-11Note Shifted register with destination equals PC is not

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-3Note The Program Counter (PC) points to the instruction being fetche

Instruction Cycle Timings 7-12 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B7.7 Multiply, and multiply accumulateThe multiply instr

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-13Note Multiply long is available only in ARM state.Note

Instruction Cycle Timings 7-14 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B7.8 Load registerA load register instruction takes a va

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-15Note Destination equals PC is not possible in Thumb sta

Instruction Cycle Timings 7-16 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B7.9 Store registerA store register has two cycles:1. Du

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-177.10 Load multiple registersA LoaD Multiple (LDM) takes

Instruction Cycle Timings 7-18 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B1 register 1 pc+2i w/h 0 (pc+2i) N cycle 0dest=pc 2 da

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-197.11 Store multiple registersSTore Multiple (STM) proce

Instruction Cycle Timings 7-20 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B7.12 Data swapData swap is similar to the load and stor

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-217.13 Software interrupt, and exception entryExceptions,

ii Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BARM7TDMI-STechnical Reference ManualCopyright © 2001 ARM Limited. All rights reser

Introduction 1-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B1.2 ARM7TDMI-S architectureThe ARM7TDMI-S processor has two instructi

Instruction Cycle Timings 7-22 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B7.14 Coprocessor data processing operationA Coprocessor

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-237.15 Load coprocessor register (from memory to coproces

Instruction Cycle Timings 7-24 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BNote Coprocessor operations are available only in ARM s

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-257.16 Store coprocessor register (from coprocessor to me

Instruction Cycle Timings 7-26 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BNote Coprocessor operations are available only in ARM s

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-277.17 Coprocessor register transfer (move from coprocess

Instruction Cycle Timings 7-28 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B7.18 Coprocessor register transfer (move from ARM regis

Instruction Cycle Timings ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 7-297.19 Undefined instructions and coprocessor absentThe u

Instruction Cycle Timings 7-30 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B7.20 Unexecuted instructionsWhen the condition code of

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 8-1Chapter 8 AC ParametersThis chapter gives the AC timing parameters of the ARM7TDMI

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-5Thumb code is typically 65% of the size of the ARM code and provides

AC Parameters 8-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B8.1 Timing diagramsThis section contains timing diagrams, as follows

AC Parameters ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 8-3Figure 8-1 Timing parameters for data accessestovtranstohtransCLKTRA

AC Parameters 8-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BNote The timing for both read and write data access are superimposed

AC Parameters ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 8-5Figure 8-3 Exception and configuration input timing8.1.4 Debug timin

AC Parameters 8-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFigure 8-4 Debug timingNote DBGBREAK is sampled on rising clock, so

AC Parameters ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 8-7Figure 8-5 Scan timingtihtctltistckentistctltihtckentovtdotohtdoCLKD

AC Parameters 8-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B8.2 AC timing parameter definitionsTable 8-1 shows target AC paramet

AC Parameters ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 8-9tovcpctlRising CLK to coprocessor control valid - 80%tohcpctlCoproce

AC Parameters 8-10 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. A-1Appendix A Signal DescriptionsThis appendix lists and describes all the ARM7TDMI-S

Introduction 1-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B1.3 ARM7TDMI-S block, core and functional diagramsThe ARM7TDMI-S proc

Signal Descriptions A-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BA.1 Signal descriptionsThe signals of the ARM7TDMI-S processor

Signal Descriptions ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. A-3CPnI Output Not coprocessor instruction. When the ARM7TDMI-S e

Signal Descriptions A-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BDBGCOMMRX Output EmbeddedICE-RT communications channel receive

Signal Descriptions ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. A-5DBGnTDOEN Output Not DBGTDO enable. When LOW, this signal deno

Signal Descriptions A-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BnRESET Input Not reset. This input signal forces the processor

Signal Descriptions ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. A-7VSSGround reference for all signals.WDATA[31:0] Output Write d

Signal Descriptions A-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. B-1Appendix B Differences Between the ARM7TDMI-S and the ARM7TDMIThis appendix descri

Differences Between the ARM7TDMI-S and the ARM7TDMI B-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BB.1 Interface signalsThe signa

Differences Between the ARM7TDMI-S and the ARM7TDMI ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. B-3CPnOPC Active LOW opcode fetch

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-7Figure 1-3 ARM7TDMI-S coreAddress registerAddressincrementerWrite dat

Differences Between the ARM7TDMI-S and the ARM7TDMI B-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BDBGRNG[1:0] EmbeddedICE-RT ran

Differences Between the ARM7TDMI-S and the ARM7TDMI ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. B-5TRANS[1:0] Next transaction ty

Differences Between the ARM7TDMI-S and the ARM7TDMI B-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BB.2 ATPG scan interfaceWhere a

Differences Between the ARM7TDMI-S and the ARM7TDMI ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. B-7B.3 Timing parametersThe timin

Differences Between the ARM7TDMI-S and the ARM7TDMI B-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BB.4 ARM7TDMI-S design consider

Differences Between the ARM7TDMI-S and the ARM7TDMI ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. B-9When you are converting an ARM

Differences Between the ARM7TDMI-S and the ARM7TDMI B-10 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFor more details on any of th

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. Index-1IndexAAbortData 2-22, 5-9, 5-45exception 2-22handler 2-22, 5-9hold time

IndexIndex-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BCoprocessorabout 4-2busy-waiting 4-8connecting 4-11–4-13data operat

IndexARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. Index-3IDCODE instruction 5-29Identification register, see ID registerInput ti

Introduction 1-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFigure 1-4 ARM7TDMI-S functional diagramCPBCPACPnICPTBITCPSEQCPnMREQC

IndexIndex-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234Bdebug status 5-61Register set 2-9Thumb state 2-12Register transfer

IndexARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. Index-5UPDATE-DR 5-28UPDATE-IR 5-32User mode 2-8WWatchpoint 5-7, 5-9, 5-

IndexIndex-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-91.4 ARM7TDMI-S instruction set summaryThis section provides a summary

Introduction 1-10 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B1.4.1 ARM instruction summaryThe ARM instruction set summary is show

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-11CompareCMP{cond} Rd, <Oprnd2>Compare negativeCMN{cond} Rd, <

Introduction 1-12 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BStack operations and restore CPSRLDM{cond}<a_mode4L> Rd{!}, &l

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-13Addressing mode 2, <a_mode2>, is shown in Table 1-3.Coprocesso

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. iiiContentsARM7TDMI-S Technical Reference ManualPrefaceAbout this document ...

Introduction 1-14 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BAddressing mode 2 (privileged), <a_mode2P>, is shown in Table

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-15Addressing mode 3 (signed byte, and halfword data transfer), <a_m

Introduction 1-16 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BAddressing mode 4 (store), <a_mode4S>, is shown in Table 1-7.A

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-17Fields, {field}, are shown in Table 1-10.Condition fields, {cond}, a

Introduction 1-18 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B1.4.2 Thumb instruction summaryThe Thumb instruction set summary is

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-19Subtract with carrySBC Rd, RsNegateNEG Rd, RsMultiplyMUL Rd, RsCompa

Introduction 1-20 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BIf C clear BCC labelIf N setBMI labelIf N clear BPL labelIf V setBVS

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-21With register offsetWordLDR Rd, [Rb, Ro]HalfwordLDRH Rd, [Rb, Ro]Sig

Introduction 1-22 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BPop registers from stackPOP <reglist>Pop registers and PC from

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-231.5 Differences between Rev 3a and Rev 4The changes incorporated in

Contentsiv Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B2.11 Reset ...

Introduction 1-24 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BBit 5 EmbeddedICE-RT disable. Use this when changing watchpoints an

Introduction ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-25For more information, see ARM7TDMI-S device identification (ID) code

Introduction 1-26 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-1Chapter 2 Programmer’s ModelThis chapter describes the programmer’s model for the

Programmer’s Model 2-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B2.1 About the programmer’s modelThe ARM7TDMI-S processor core i

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-32.2 Processor operating statesThe ARM7TDMI-S processor has two

Programmer’s Model 2-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B2.3 Memory formatsThe ARM7TDMI-S processor views memory as a li

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-5Figure 2-2 Little-endian addresses of bytes within wordsHigher

Programmer’s Model 2-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B2.4 Instruction lengthInstructions are either: • 32 bits long (

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-72.5 Data typesThe ARM7TDMI-S processor supports the following d

ContentsARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. v5.26 Coupling breakpoints and watchpoints ...

Programmer’s Model 2-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B2.6 Operating modesThe ARM7TDMI-S processor has seven operating

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-92.7 RegistersThe ARM7TDMI-S processor has a total of 37 registe

Programmer’s Model 2-10 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BBanked registers have a mode identifier that shows to which Us

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-11Figure 2-3 Register organization in ARM stateARM state general

Programmer’s Model 2-12 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B2.7.2 The Thumb state register setThe Thumb state register set

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-13Figure 2-4 Register organization in Thumb state2.7.3 The relat

Programmer’s Model 2-14 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFigure 2-5 Mapping of Thumb state registers onto ARM state reg

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-15You can use special variants of the MOV instruction to transfe

Programmer’s Model 2-16 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B2.8 The program status registersThe ARM7TDMI-S core contains a

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-172.8.2 The control bitsThe bottom eight bits of a PSR are known

Contentsvi Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B

Programmer’s Model 2-18 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BNote If you program an illegal value into M[4:0], the processo

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-192.9 ExceptionsExceptions arise whenever the normal flow of a p

Programmer’s Model 2-20 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B2.9.2 Entering an exceptionWhen handling an exception the ARM7

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-21Note Exceptions are always handled in ARM state. When the proc

Programmer’s Model 2-22 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BIrrespective of whether exception entry is from ARM state, or

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-23The abort mechanism enables the implementation of a demand-pag

Programmer’s Model 2-24 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFor more information about undefined instructions, see the ARM

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-25• When FIQs are enabled and a Data Abort occurs at the same ti

Programmer’s Model 2-26 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B2.10 Interrupt latenciesInterrupt latencies are described in:•

Programmer’s Model ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-272.11 ResetWhen the nRESET signal goes LOW, the ARM7TDMI-S proc

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. viiList of TablesARM7TDMI-S Technical Reference ManualChange history ...

Programmer’s Model 2-28 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-1Chapter 3 Memory InterfaceThis chapter describes the memory interface on the ARM7T

Memory Interface 3-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B3.1 About the memory interfaceThe ARM7TDMI-S processor has a Von

Memory Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-33.2 Bus interface signalsThe signals in the ARM7TDMI-S processor

Memory Interface 3-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B3.3 Bus cycle types The ARM7TDMI-S processor bus interface is pip

Memory Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-5The ARM7TDMI-S processor has four basic types of memory cycle:Non

Memory Interface 3-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFigure 3-2 Nonsequential memory cycleThe ARM7TDMI-S processor can

Memory Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-73.3.2 Sequential cyclesSequential cycles perform burst transfers

Memory Interface 3-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFigure 3-4 Sequential access cycles3.3.3 Internal cyclesDuring an

Memory Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-9Figure 3-5 Merged I-S cycleNote When designing a memory controlle

List of Tablesviii Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BTable 3-7 Word accesses ...

Memory Interface 3-10 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B3.4 Addressing signalsThe address class signals are described in

Memory Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-11The size of transfer does not change during a burst of S cycles.

Memory Interface 3-12 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B3.4.6 CPTBITCPTBIT indicates the operating state of the ARM7TDMI

Memory Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-133.5 Data timed signalsThe data timed signals are described in th

Memory Interface 3-14 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B3.5.4 Byte and halfword accessesThe ARM7TDMI-S processor indicat

Memory Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-15The fields extracted by the ARM7TDMI-S processor are shown in Ta

Memory Interface 3-16 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFigure 3-6 Data replicationABARM7TDMI-S processorbyte writeMemor

Memory Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-173.6 Using CLKEN to control bus cyclesThe pipelined nature of the

Memory Interface 3-18 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 4-1Chapter 4 Coprocessor InterfaceThis chapter describes the ARM7TDMI-S coprocessor i

ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. ixList of FiguresARM7TDMI-S Technical Reference ManualKey to timing diagram conventio

Coprocessor Interface 4-2 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B4.1 About coprocessorsThe ARM7TDMI-S processor instruction s

Coprocessor Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 4-34.1.1 Coprocessor availabilityYou can connect up to 16 copro

Coprocessor Interface 4-4 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B4.2 Coprocessor interface signalsThe signals used to interfa

Coprocessor Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 4-54.3 Pipeline-following signalsEvery coprocessor in the syste

Coprocessor Interface 4-6 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B4.4 Coprocessor interface handshakingThe ARM7TDMI-S core and

Coprocessor Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 4-74.4.3 Coprocessor signalingThe coprocessor signals as follow

Coprocessor Interface 4-8 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B4.4.4 Consequences of busy-waitingA busy-waited coprocessor

Coprocessor Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 4-94.4.6 Coprocessor data operationsCoprocessor data operations

Coprocessor Interface 4-10 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234BFigure 4-4 Coprocessor load sequenceADD SWINETSTLDCSUBTSTLD

Coprocessor Interface ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 4-114.5 Connecting coprocessorsA coprocessor in an ARM7TDMI-S p