ARM ARM7TDMI User Manual Page 77
- Page / 242
- Table of contents
- BOOKMARKS
Rated. / 5. Based on customer reviews
Memory Interface
ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 3-7
3.3.2 Sequential cycles
Sequential cycles perform burst transfers on the bus. You can use this information to
optimize the design of a memory controller interfacing to a burst memory device, such
as a DRAM.
During a sequential cycle, the ARM7TDMI-S processor requests a memory location
that is part of a sequential burst. If this is the first cycle in the burst, the address can be
the same as the previous internal cycle. Otherwise the address is incremented from the
previous cycle:
• for a burst of word accesses, the address is incremented by 4 bytes
• for a burst of halfword accesses, the address is incremented by 2 bytes.
Bursts of byte accesses are not possible.
A burst always starts with an N cycle or a merged I-S cycle (see Merged I-S cycles on
page 3-8), and continues with S cycles. A burst comprises transfers of the same type.
The ADDR[31:0] signal increments during the burst. The other address class signals
remain the same throughout the burst.
The types of burst are shown in Table 3-2.
All accesses in a burst are of the same width, direction, and protection type. For more
details, see Addressing signals on page 3-10.
An example of a burst access is shown in Figure 3-4 on page 3-8.
Table 3-2 Burst types
Burst type Address increment Cause
Word read 4 bytes ARM7TDMI-S code fetches, or LDM instruction
Word write 4 bytes STM instruction
Halfword read 2 bytes Thumb code fetches
- ARM7TDMI-S 1
- Contents 3
- Chapter 3 Memory Interface 4
- Chapter 6 ETM Interface 5
- Chapter 8 AC Parameters 5
- List of Tables 7
- List of Figures 10
- • Feedback on page xvi 11
- About this document 12
- Preface 13
- Other publications 15
- Architecture 15
- Feedback 16
- Chapter 1 17
- Introduction 17
- 1.2 ARM7TDMI-S architecture 20
- Figure 1-3 ARM7TDMI-S core 23
- 1.4.1 ARM instruction summary 26
- [Rn, #+/-12bit_Offset] 29
- [Rn, +/-Rm] 29
- [Rn, #+/-12bit_Offset]! 29
- [Rn, +/-Rm]! 29
- , is shown in Table 1-4 30
- [Rn, #+/-8bit_Offset] 31
- Register 31
- [Rn, #+/-(8bit_Offset*4)] 32
- Post-indexed 32
- Fields 33
- , are shown in Table 1-10 33
- Condition fields 33
- , are shown in Table 1-11 33
- Halfword 36
- POP <reglist> 38
- POP <reglist, PC> 38
- SWI 8bit_Imm 38
- 0x7F1F0F0F 40
- Chapter 2 43
- Programmer’s Model 43
- 2.3 Memory formats 46
- 2.4 Instruction length 48
- 2.5 Data types 49
- 2.6 Operating modes 50
- 2.7 Registers 51
- Table 2-2 PSR mode bit values 59
- MOV PC, R14 61
- MOVS PC, R14_svc 61
- MOVS PC, R14_und 61
- SUBS PC, R14_abt, #4 61
- SUBS PC, R14_fiq, #4 62
- SUBS PC, R14_irq, #4 62
- SUBS PC, R14_abt, #8 62
- UNPREDICTABLE 62
- SUBS PC,R14_fiq,#4 63
- SUBS PC,R14_abt,#8 65
- MOVS PC,R14_und 65
- 2.10 Interrupt latencies 68
- 2.11 Reset 69
- Chapter 3 71
- Memory Interface 71
- 3.2 Bus interface signals 73
- 3.3 Bus cycle types 74
- Table 3-2 Burst types 77
- Figure 3-5 Merged I-S cycle 79
- 3.4 Addressing signals 80
- 3.4.6 CPTBIT 82
- 3.5 Data timed signals 83
- Figure 3-6 Data replication 86
- Figure 3-7 Use of CLKEN 87
- Chapter 4 89
- 4.1 About coprocessors 90
- Table 4-2 Handshaking signals 94
- Signal Direction Meaning 94
- 4.5 Connecting coprocessors 99
- Coprocessor Interface 100
- 4.7 Undefined instructions 103
- 4.8 Privileged instructions 104
- Chapter 5 105
- Debugging Your System 105
- 5.2 Controlling debugging 109
- 5.3 Entry into debug state 111
- Figure 5-3 Debug state entry 112
- ARM7TDMI-Smacrocell 115
- 5.4 Debug interface 116
- EmbeddedICE-RT 118
- 5.7 Disabling EmbeddedICE-RT 120
- 5.9 Monitor mode debugging 122
- 0 RW...100 124
- MRC CP14, 0, Rd, C0, C0 125
- MCR CP14, 0, Rn, C1, C0 125
- MRC CP14, 0, Rd, C1, C0 126
- 5.12 The TAP controller 130
- 5.13 Public JTAG instructions 132
- 011112272831 135
- Part number 135
- Manufacturer identity 1 135
- 0x7f1f0f0f 136
- 5.15 Scan timing 140
- 31 DATA[30] Input/output 142
- 32 DATA[31] Input/output 142
- 33 DBGBREAK Input 142
- Number Signal Type 142
- 5.17 Exit from debug state 146
- 0 E0802000; ADD R2, R0, R0 148
- 1 E1826001; ORR R6, R2, R1 148
- MOV R0, R0 148
- SUB PC, PC, #28 148
- - (4 + N + 3S) 150
- - (3 + N + 3S) 150
- 8 67 5 34 2 01 154
- 5.21 Programming breakpoints 157
- 0xffffffff 158
- 0xdfffdfff 158
- 0x00000000 158
- 5.22 Programming watchpoints 159
- 5.23 Abort status register 160
- 5.24 Debug control register 161
- 5.25 Debug status register 164
- 5.27 EmbeddedICE-RT timing 169
- Chapter 6 171
- ETM Interface 171
- 6.1 About the ETM interface 172
- 6.4 Clocks and resets 176
- 6.5 Debug request wiring 177
- Chapter 7 179
- Instruction Cycle Timings 179
- MOV PC,R14 185
- STM..{R14} LDM..{PC} 185
- 7.4 Thumb branch with link 186
- 7.5 Branch and exchange 187
- 7.6 Data operations 188
- 7.8 Load register 192
- 7.9 Store register 194
- 7.10 Load multiple registers 195
- 7.11 Store multiple registers 197
- 7.12 Data swap 198
- 7.20 Unexecuted instructions 208
- Chapter 8 209
- AC Parameters 209
- 8.1 Timing diagrams 210
- Figure 8-2 Coprocessor timing 212
- 8.1.4 Debug timing 213
- 8.1.5 Scan timing 214
- Figure 8-5 Scan timing 215
- Appendix A 219
- Signal Descriptions 219
- A.1 Signal descriptions 220
- Appendix B 227
- ARM7TDMI 227
- B.1 Interface signals 228
- B.2 ATPG scan interface 232
- B.3 Timing parameters 233
Related products and manuals for Processors ARM ARM7TDMI
Processors ARM ARM7TDMI User Manual
(43 pages)
(43 pages)
© 2020, manymanuals.com. All rights reserved. | 1.223 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comments to this Manuals