Introduction
1-16 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B
Addressing mode 4 (store),
<a_mode4S>
, is shown in Table 1-7.
Addressing mode 5 (coprocessor data transfer),
<a_mode5>
, is shown in Table 1-8.
Operand 2,
<Oprnd2>
, is shown in Table 1-9.
Table 1-7 Addressing mode 4 (store)
Addressing mode Stack type
IA Increment after EA Empty ascending
IB Increment before FA Full ascending
DA Decrement after ED Empty descending
DB Decrement before FD Full descending
Table 1-8 Addressing mode 5
Operation Assembler
Immediate offset
[Rn, #+/-(8bit_Offset*4)]
Pre-indexed
[Rn, #+/-(8bit_Offset*4)]!
Post-indexed
[Rn], #+/-(8bit_Offset*4)
Table 1-9 Operand 2
Operation Assembler
Immediate value
#32bit_Imm
Logical shift left
Rm LSL #5bit_Imm
Logical shift right
Rm LSR #5bit_Imm
Arithmetic shift right
Rm ASR #5bit_Imm
Rotate right
Rm ROR #5bit_Imm
Register
Rm
Logical shift left
Rm LSL Rs
Logical shift right
Rm LSR Rs
Comments to this Manuals