ARM ARM7TDMI User Manual Page 63
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Programmer’s Model
ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 2-21
Note
Exceptions are always handled in ARM state. When the processor is in Thumb state and
an exception occurs, the switch to ARM state takes place automatically when the
exception vector address is loaded into the PC.
2.9.3 Leaving an exception
When an exception is completed, the exception handler must:
1. Move the LR, minus an offset to the PC. The offset varies according to the type
of exception, as shown in Table 2-3 on page 2-19.
2. Copy the SPSR back to the CPSR.
3. Clear the interrupt disable flags that were set on entry.
Note
The action of restoring the CPSR from the SPSR automatically restores the T, F, and I
bits to whatever value they held immediately prior to the exception.
2.9.4 Fast interrupt request
The Fast Interrupt Request (FIQ) exception supports data transfers or channel
processes. In ARM state, FIQ mode has eight private registers to remove the need for
register saving (this minimizes the overhead of context switching).
An FIQ is externally generated by taking the nFIQ signal input LOW.
Irrespective of whether exception entry is from ARM state, or from Thumb state, an FIQ
handler returns from the interrupt by executing:
SUBS PC,R14_fiq,#4
You can disable FIQ exceptions within a privileged mode by setting the CPSR F flag.
When the F flag is clear, the ARM7TDMI-S checks for a LOW level on the output of
the FIQ synchronizer at the end of each instruction.
2.9.5 Interrupt request
The Interrupt Request (IRQ) exception is a normal interrupt caused by a LOW level on
the nIRQ input. IRQ has a lower priority than FIQ, and is masked on entry to an FIQ
sequence. You can disable IRQ at any time, by setting the I bit in the CPSR from a
privileged mode.
- ARM7TDMI-S 1
- Contents 3
- Chapter 3 Memory Interface 4
- Chapter 6 ETM Interface 5
- Chapter 8 AC Parameters 5
- List of Tables 7
- List of Figures 10
- • Feedback on page xvi 11
- About this document 12
- Preface 13
- Other publications 15
- Architecture 15
- Feedback 16
- Chapter 1 17
- Introduction 17
- 1.2 ARM7TDMI-S architecture 20
- Figure 1-3 ARM7TDMI-S core 23
- 1.4.1 ARM instruction summary 26
- [Rn, #+/-12bit_Offset] 29
- [Rn, +/-Rm] 29
- [Rn, #+/-12bit_Offset]! 29
- [Rn, +/-Rm]! 29
- , is shown in Table 1-4 30
- [Rn, #+/-8bit_Offset] 31
- Register 31
- [Rn, #+/-(8bit_Offset*4)] 32
- Post-indexed 32
- Fields 33
- , are shown in Table 1-10 33
- Condition fields 33
- , are shown in Table 1-11 33
- Halfword 36
- POP <reglist> 38
- POP <reglist, PC> 38
- SWI 8bit_Imm 38
- 0x7F1F0F0F 40
- Chapter 2 43
- Programmer’s Model 43
- 2.3 Memory formats 46
- 2.4 Instruction length 48
- 2.5 Data types 49
- 2.6 Operating modes 50
- 2.7 Registers 51
- Table 2-2 PSR mode bit values 59
- MOV PC, R14 61
- MOVS PC, R14_svc 61
- MOVS PC, R14_und 61
- SUBS PC, R14_abt, #4 61
- SUBS PC, R14_fiq, #4 62
- SUBS PC, R14_irq, #4 62
- SUBS PC, R14_abt, #8 62
- UNPREDICTABLE 62
- SUBS PC,R14_fiq,#4 63
- SUBS PC,R14_abt,#8 65
- MOVS PC,R14_und 65
- 2.10 Interrupt latencies 68
- 2.11 Reset 69
- Chapter 3 71
- Memory Interface 71
- 3.2 Bus interface signals 73
- 3.3 Bus cycle types 74
- Table 3-2 Burst types 77
- Figure 3-5 Merged I-S cycle 79
- 3.4 Addressing signals 80
- 3.4.6 CPTBIT 82
- 3.5 Data timed signals 83
- Figure 3-6 Data replication 86
- Figure 3-7 Use of CLKEN 87
- Chapter 4 89
- 4.1 About coprocessors 90
- Table 4-2 Handshaking signals 94
- Signal Direction Meaning 94
- 4.5 Connecting coprocessors 99
- Coprocessor Interface 100
- 4.7 Undefined instructions 103
- 4.8 Privileged instructions 104
- Chapter 5 105
- Debugging Your System 105
- 5.2 Controlling debugging 109
- 5.3 Entry into debug state 111
- Figure 5-3 Debug state entry 112
- ARM7TDMI-Smacrocell 115
- 5.4 Debug interface 116
- EmbeddedICE-RT 118
- 5.7 Disabling EmbeddedICE-RT 120
- 5.9 Monitor mode debugging 122
- 0 RW...100 124
- MRC CP14, 0, Rd, C0, C0 125
- MCR CP14, 0, Rn, C1, C0 125
- MRC CP14, 0, Rd, C1, C0 126
- 5.12 The TAP controller 130
- 5.13 Public JTAG instructions 132
- 011112272831 135
- Part number 135
- Manufacturer identity 1 135
- 0x7f1f0f0f 136
- 5.15 Scan timing 140
- 31 DATA[30] Input/output 142
- 32 DATA[31] Input/output 142
- 33 DBGBREAK Input 142
- Number Signal Type 142
- 5.17 Exit from debug state 146
- 0 E0802000; ADD R2, R0, R0 148
- 1 E1826001; ORR R6, R2, R1 148
- MOV R0, R0 148
- SUB PC, PC, #28 148
- - (4 + N + 3S) 150
- - (3 + N + 3S) 150
- 8 67 5 34 2 01 154
- 5.21 Programming breakpoints 157
- 0xffffffff 158
- 0xdfffdfff 158
- 0x00000000 158
- 5.22 Programming watchpoints 159
- 5.23 Abort status register 160
- 5.24 Debug control register 161
- 5.25 Debug status register 164
- 5.27 EmbeddedICE-RT timing 169
- Chapter 6 171
- ETM Interface 171
- 6.1 About the ETM interface 172
- 6.4 Clocks and resets 176
- 6.5 Debug request wiring 177
- Chapter 7 179
- Instruction Cycle Timings 179
- MOV PC,R14 185
- STM..{R14} LDM..{PC} 185
- 7.4 Thumb branch with link 186
- 7.5 Branch and exchange 187
- 7.6 Data operations 188
- 7.8 Load register 192
- 7.9 Store register 194
- 7.10 Load multiple registers 195
- 7.11 Store multiple registers 197
- 7.12 Data swap 198
- 7.20 Unexecuted instructions 208
- Chapter 8 209
- AC Parameters 209
- 8.1 Timing diagrams 210
- Figure 8-2 Coprocessor timing 212
- 8.1.4 Debug timing 213
- 8.1.5 Scan timing 214
- Figure 8-5 Scan timing 215
- Appendix A 219
- Signal Descriptions 219
- A.1 Signal descriptions 220
- Appendix B 227
- ARM7TDMI 227
- B.1 Interface signals 228
- B.2 ATPG scan interface 232
- B.3 Timing parameters 233
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