Introduction
ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. 1-15
Addressing mode 3 (signed byte, and halfword data transfer),
<a_mode3>
, is shown in
Table 1-5.
Addressing mode 4 (load),
<a_mode4L>
, is shown in Table 1-6.
[Rn], +/-Rm, ASR #5bit_shift_imm
[Rn], +/-Rm, ROR #5bit_shift_imm
[Rn, +/-Rm, RRX]
Table 1-5 Addressing mode 3
Operation Assembler
Immediate offset
[Rn, #+/-8bit_Offset]
Pre-indexed
[Rn, #+/-8bit_Offset]!
Post-indexed
[Rn], #+/-8bit_Offset
Register
[Rn, +/-Rm]
Pre-indexed
[Rn, +/-Rm]!
Post-indexed
[Rn], +/-Rm
Table 1-6 Addressing mode 4 (load)
Addressing mode Stack type
IA Increment after FD Full descending
IB Increment before ED Empty descending
DA Decrement after FA Full ascending
DB Decrement before EA Empty ascending
Table 1-4 Addressing mode 2 (privileged) (continued)
Operation Assembler
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