Debugging Your System
5-56 Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B
5.23 Abort status register
Only bit 0 of this 32 bit read/write register is used. It determines whether an abort
exception entry was caused by a breakpoint, a watchpoint, or a real abort. The format is
shown in Figure 5-14.
Figure 5-14 Debug abort status register
This bit is set when the ARM7TDMI-S core takes a Prefetch or Data Abort as a result
of a breakpoint or watchpoint. If, on a particular instruction or data fetch, both the
Debug Abort and the external Abort signal are asserted, the external Abort takes
priority, and the D/jointfilesconvert/457765/bgAbt bit is not set. Once set, D/jointfilesconvert/457765/bgAbt remains set until reset by the
user. The register is accessed by
MRC
and
MCR
instructions.
D/jointfilesconvert/457765/bgAbt
0
SBZ/RAZ
31:1
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