ARM ARM7TDMI User Manual download pdf (Page 87)

Memory Interface

3.6 Using CLKEN to control bus cycles

The pipelined nature of the ARM7TDMI-S processor bus interface means that there is

a distinction between clock cycles and bus cycles. CLKEN can be used to stretch a bus

cycle, so that it lasts for many clock cycles. The CLKEN input extends the timing of

bus cycles in increments of complete CLK cycles:

• when CLKEN is HIGH on the rising edge of CLK, a bus cycle completes

• when CLKEN is sampled LOW, the bus cycle is extended.

In the pipeline, the address class signals and the memory request signals are ahead of

the data transfer by one bus cycle. In a system using CLKEN this can be more than one

CLK cycle. This is illustrated in Figure 3-7, which shows CLKEN being used to extend

a nonsequential cycle. In the example, the first N cycle is followed by another N cycle

to an unrelated address, and the address for the second access is broadcast before the

first access completes.

Figure 3-7 Use of CLKEN

Note

When designing a memory controller, you are strongly advised to sample the values of

TRANS[1:0] and the address class signals only when CLKEN is HIGH. This ensures

that the state of the memory controller is not accidentally updated during a bus cycle.

Address 1Address-class signals

TRANS[1:0]

RDATA[31:0]

(read)

Read data1

Address 2

Read data2

First bus cycle

Second bus cycle

CLK

Next address

Ncycle Ncycle Next cycle type

CLKEN

1 2 ... 82 83 84 85 86 87 88 89 90 91 92 ... 241 242

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ARM ARM7TDMI User Manual Page 87