ARM VERSION 1.2 Datasheet download pdf (Page 38)

ARMulator Basics

2.6.6 Pagetable module and protection units

Processors such as ARM740T

™

and ARM940T

™

have a PU.

A PU uses a set of protection regions. The base and size of each protection region is

stored in registers in the PU. On reset, the page table module initializes the PU.

For example, the default configuration details given above define a single region,

region 0. This region is marked as read/write, cacheable, and bufferable. It occupies the

whole address range, 0 to 4GB.

ARM740T PU

For an ARM740T, the PU is initialized as follows:

• The P, C, and W bits are set in the configuration register, register 1, to enable the

protection unit, the cache and the write buffer.

• The cacheable register, register 2, is initialized to 1, marking region 0 as

cacheable.

• The write buffer control register, register 3, is initialized to 1, marking region 0 as

bufferable.

• The protection register, register 5, is initialized to 3, marking region 0 as

read/write access. This is configured in the

AccessPermissions

line.

• The protection region base and size register for region 0 is initialized to

0x3F

marking the size of region 0 as 4GB and marking the region as enabled. The

protection region base and size register for region 0 is part of register 6. Register 6

is actually a set of eight registers, each being the protection region base and size

further details.

• The protection region base and size register for region 1 is initialized to set the

size of region 0 as 128MB and enabled.

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 175 176

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ARM VERSION 1.2 Datasheet Page 38