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System Control
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Figure 4-2 shows the CPUID bit assignments.
Figure 4-2 CPUID bit assignments
Table 4-3 shows the CPUID bit assignments.
4.3.3 Auxiliary Fault Status Register, AFSR
The AFSR characteristics are:
Purpose Specifies additional system fault information to software.
Usage Constraints The AFSR flags map directly onto the AUXFAULT inputs of the
processor, and a single-cycle high level on an external pin causes the
corresponding AFSR bit to become latched as one. The bit can only be
cleared by writing a one to the corresponding AFSR bit.
When an AFSR bit is written or latched as one, an exception does not
occur. To make use of AUXFAULT input signals, software must poll the
AFSR.
Configurations This register is available in all processor configurations.
Attributes See the register summary in Table 4-1 on page 4-3.
Figure 4-3 shows the AFSR bit assignments.
Figure 4-3 AFSR bit assignments
Table 4-4 shows the AFSR bit assignments.
31 16 15 4 3 0
IMPLEMENTER
REVISIONPARTNO
24 23 20 19
VARIANT (Constant)
Table 4-3 CPUID bit assignments
Bits NAME Function
[31:24] IMPLEMENTER Indicates implementer:
0x41
= ARM
[23:20] VARIANT Indicates processor revision:
0x2
= Revision 2
[19:16] (Constant) Reads as
0xF
[15:4] PARTNO Indicates part number:
0xC23
= Cortex-M3
[3:0] REVISION Indicates patch release:
0x1
= Patch 1.
AUXFAULT
31 0
Table 4-4 AFSR bit assignments
Bits Name Function
[31:0] AUXFAULT Latched version of the AUXFAULT inputs.
- Technical Reference Manual 1
- Cortex-M3 2
- Contents 3
- List of Tables 5
- List of Figures 7
- • About this book on page x 9
- • Feedback on page xiii 9
- About this book 10
- Preface 11
- Other publications 12
- Feedback 13
- Chapter 1 14
- Introduction 14
- 1.1 About the processor 15
- 1.2 Features 16
- 1.3 Interfaces 17
- 1.4 Configurable options 18
- 1.5 Product documentation 19
- 1.6 Product revisions 22
- 0xE000ED14 23
- Chapter 2 25
- Functional Description 25
- 2.1 About the functions 26
- 2.2 Interfaces 28
- Chapter 3 31
- Programmers Model 31
- 3.3 Instruction set summary 34
- — STKALIGN bit to 1 40
- — UNALIGN_TRP bit to 1 40
- 3.4 System address map 41
- LDRH, STR, STRH 42
- 3.5 Write buffer 44
- 3.6 Exclusive monitor 45
- 3.7 Bit-banding 46
- Figure 3-2 Bit-band mapping 47
- 3.9 Exceptions 50
- Chapter 4 52
- System Control 52
- 4.1 About system control 53
- 4.2 Register summary 54
- 4.3 Register descriptions 56
- Chapter 5 58
- Memory Protection Unit 58
- 5.1 About the MPU 59
- 5.3 MPU programmers model 61
- Chapter 6 62
- 6.1 About the NVIC 63
- 6.3 NVIC programmers model 65
- Chapter 7 67
- 7.1 About debug 68
- 0xE000ED00 69
- 0xE00FF000 70
- 7.2 About the AHB-AP 72
- 7.3.2 FPB programmers model 76
- Chapter 8 77
- 8.1 About the DWT 78
- 8.3 DWT Programmers Model 80
- 0x40000000 81
- 0x4F000000 81
- 0x10000000 81
- 0x1F000000 81
- Chapter 9 82
- 9.1 About the ITM 83
- 9.3 ITM programmers model 85
- PRIVMASK 86
- Chapter 10 87
- 10.1 About the ETM 88
- Figure 10-1 ETM block diagram 89
- 10.2.9 Operation 94
- 10.3 ETM Programmers model 95
- Embedded Trace Macrocell 100
- ID072410 Non-Confidential 100
- Reserved 102
- 26 25 24 102
- Trace control enable 102
- Reserved, RAZ 106
- ETM powered up 106
- TRIGGER output value 107
- Chapter 11 109
- Trace Port Interface Unit 109
- 11.1 About the Cortex-M3 TPIU 110
- 11.3 TPIU programmers model 113
- TRIGGER input value 116
- Appendix A 122
- Revisions 122
- Glossary 129
- 0x00000000 132
- 0x1FFFFFFFF 132
- 0xE0040000 133
- 0xE00FFFFF 133
- 0x1FFFFFFF 133
- 0xE0000000 134
- 0xE003FFFF 134
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