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Hardware Description
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3.5.3 Peripheral clocks
Table 3-11 lists the other memory and peripheral clocks on the PB926EJ-S.
For more detail on the clocking system, see the files in the
Schematics
directory of the
CD supplied with the PB926EJ-S.
3.5.4 Clock multiplexor logic
Figure 3-23 on page 3-55 shows the clock multiplexor switches and the effect of the
HCLKCTRL[4:0] signals.
Note
The HCLKx_L2S and HCLKx_L2F clocks must be driven from the same reference
source in the RealView Logic Tile. The HCLKx_F2S and HCLKx_F2F clocks are
driven from the same source in the PB926EJ-S FPGA. Two signals are used for each
clock for loading purposes and to allow for future expansion.
Table 3-11 PB926EJ-S clocks and clock control signals
Clock signal Frequency Description Source
AACIBITCLK 12.288MHz This is the synchronization clock from the audio CODEC. The
clock is an input to the AACI PrimeCell.
Crystal
oscillator
CLCDCLKEXT 6–50MHz The clock for PL110 CLCD Controller in the development chip
can be derived from this input.
ICS307
OSC4
ETHLCLK AHB M2 ETHLCLK is used to synchronize data transfers between the
external controller and the FPGA. (The Ethernet controller uses a
25MHz crystal for clocking signals to and from the Ethernet
connector.)
HCLKM2
(typically
OSC0)
MPMCCLK[4:0] - The dynamic memory clocks from the MPMC in the development
chip. This is a buffered version of HCLK.
MPMC
controller
PCICLK - This is the clock from the PCI backplane.
SCIREFCLKEXT 24MHz The clock for PL131 SCI in the development chip can be derived
from this input. This is a buffered version of REFCLK24MHZ.
24MHz
reference
SMCLK[2:0] - The static memory clocks from the SSMC in the development
chip. This is HCLK divided by 1, 2, or 3.
SSMC
controller
- ARM926EJ-S 1
- CE Declaration of Conformity 4
- Contents 5
- List of Tables 10
- List of Figures 13
- User Guide 13
- • Feedback on page xxv 17
- About this manual 18
- Preface 19
- Feedback 25
- Chapter 1 27
- Introduction 27
- 1.1 About the PB926EJ-S 28
- Figure 1-1 PB926EJ-S layout 29
- 1.2 PB926EJ-S architecture 30
- PB926EJ-S 32
- 1.3 Precautions 35
- Chapter 2 37
- Getting Started 37
- 2.2.2 LED indicators 41
- SET BOOTSCRIPT 43
- Figure 2-2 JTAG connection 44
- 2.5 Supplying power 49
- Q, quit, qui, qu, or q 50
- Release_ARM_Little_Endian 55
- Chapter 3 63
- • USB interface on page 3-92 64
- • UART interface on page 3-88 64
- 0xFFFF0000 69
- Figure 3-4 AHB map 75
- Figure 3-6 Memory devices 77
- 3.2 FPGA 79
- 0x200000 81
- 0x400000 81
- 0x600000 81
- Progcards 83
- 3.3 Reset controller 84
- 3.3.4 Reset signals 91
- 3.4 Power supply control 95
- 3.5 Clock architecture 97
- Hardware Description 100
- ARM926EJ-S Dev. Chip 101
- Schematics 116
- Figure 3-24 Audio interface 119
- 3.7 Character LCD controller 121
- Figure 3-25 Character display 122
- 3.8 CLCDC interface 123
- Figure 3-26 Display interface 124
- Figure 3-27 DMA channels 128
- 3.10 Ethernet interface 130
- 3.11 GPIO interface 133
- 3.12 Interrupts 134
- Figure 3-31 KMI block diagram 136
- Figure 3-32 MMI interface 139
- 3.15 PCI interface 141
- 3.16 Serial bus interface 142
- Figure 3-35 SCI block diagram 144
- Figure 3-36 SSP block diagram 146
- 3.19 User switches and LEDs 149
- 3.20 UART interface 150
- Figure 3-39 UART0 interface 151
- Reference Manual 152
- 3.21 USB interface 154
- TransDimension OTG243 155
- Chapter 4 167
- Programmer’s Reference 167
- 4.1 Memory map 169
- Development Chip 173
- 0x101E0000 177
- 0x34000000–0x37FFFFFF 177
- Booting from NOR flash 1 178
- LOW) are shown in Figure 4-3 179
- Memory banks 182
- 0x10000000 183
- 0x10000004 187
- 4.3.3 LED Register, SYS_LED 188
- Use the SYS_LED register at 188
- 0x1000000C 189
- 0x1000001C 189
- 0x0000A05F 189
- 0x10000020 190
- Figure 4-10 SYS_CFGDATA1 191
- SYS_CFGDATA2 at address 192
- 0x10000040 197
- 0x10000044 197
- 0x10000048 197
- 0x1000004C 198
- 0x10000050 198
- 0x10000054 200
- 0x10000058 200
- 0x1000005C 202
- 0x10000060 202
- 0x10000064 203
- 0x10000068 203
- 0x1000006C 203
- 0x1000008C 205
- 0x1000009C 205
- 0x100000C0 206
- 0x100000C4 206
- 0x100000C8 206
- 0x100000CC 206
- 0x100000D0 206
- 0x101D0000 207
- 0x10004000 208
- 0x10008000 210
- 0x10120000 213
- 0x10130000 218
- 0x10010000 221
- 0x101E4000 222
- 0x101E5000 222
- 0x101E6000 222
- 0x101E7000 222
- 0x101E8000 222
- 0x10140000 223
- 0x10003000 223
- 0x10003020 228
- 0x10003024 228
- PIC_SCR31 231
- // . . 232
- 0x10006000 233
- 0x10007000 233
- 0x40000000 234
- 4.14 MOVE video coprocessor 235
- 0x10005000 236
- 0x1000B000 236
- 0x10110000 237
- 4.17 PCI controller 240
- 0x41000000 241
- 0x6FFFFFFF 241
- 0x1000101C 242
- 0x10001010 242
- 0x10001014 242
- 0x10001018 242
- PCI_SMAPx registers 244
- 4.17.2 PCI configuration 245
- 0x42000000 246
- 0x10002000 252
- 0x10002004 252
- 0xA0 0xA1 253
- 0xA2 0xA3 253
- 0xD0 0xD1 253
- 0x101F0000 254
- 0x1000A000 254
- 0x101F4000 255
- 0x10100000 257
- 0x303121 260
- 0x101E000 261
- 0x101E2000 262
- 0x101E2020 262
- 0x101E3000 262
- 0x101E3020 262
- 0x101F1000 263
- 0x101F2000 263
- 0x101F3000 263
- 0x10009000 263
- 0x10020000 265
- 0x10020080 265
- 0x10020100 265
- 0x101E1000 267
- Appendix A 269
- Signal Descriptions 269
- A.2 Smart Card interface 271
- A.3 UART interface 273
- A.4 USB interface 274
- A.5 Audio CODEC interface 275
- Figure A-8 MMC card 276
- A.7 CLCD display interface 278
- A.8 VGA display interface 281
- A.9 GPIO interface 282
- A.11 Ethernet interface 284
- A.12.2 HDRY signals 290
- A.12.3 HDRZ 294
- 2 USBDM 304
- 3 USBDP 304
- A.13.4 Trace connector pinout 305
- SSP connector 306
- Appendix B 309
- Specifications 309
- B.1 Electrical specification 310
- B.2 Clock rate restrictions 313
- B.2.1 AHB bus timing 314
- 35MHz for a 314
- of 28.5ns) 314
- B.3 Mechanical details 317
- Appendix C 319
- Enable V+ 328
- Selftest 329
- Y positions 330
- C.4 Connectors 333
- C.5 Mechanical layout 337
- Appendix D 339
- PCI Backplane and Enclosure 339
- PCI controller on page 4-74) 341
- D.2 Backplane hardware 344
- D.2.1 JTAG signals 347
- D.3 Connectors 348
- D.3.3 JTAG connector 350
- Appendix E 351
- Memory Expansion Boards 351
- Expansion connector J13 352
- Expansion connector 353
- E.2 Fitting a memory board 355
- E.3 EEPROM contents 356
- Contents Contents 358
- E.4 Connector pinout 363
- E.5 Mechanical layout 370
- Appendix F 371
- RealView Logic Tile 371
- F.3 Header connectors 374
- Clock generators and crystals 380
- 0x14000000 382
- 0x1F000000 382
- Appendix G 385
- ARM-ARM-DIR 389
- VPB926EJ-S USB 389
- G.4.1 Global Properties 395
- G.4.2 Device Properties 396
- G.4.3 Semihosting Properties 397
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