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Programmer’s Reference

4.8 Direct Memory Access Controller and mapping registers

The PrimeCell Direct Memory Access Controller (DMAC) is an AMBA compliant SoC

peripheral that is developed, tested, and licensed by ARM Limited. The DMAC is

located in the ARM926EJ-S PXP Development Chip and three DMA mapping registers

are located in the FPGA.

Sixteen peripheral DMA interfaces are provided by the PrimeCell DMAC, of which ten

are used by the ARM926EJ-S PXP Development Chip peripherals (UART0–3, SCI, and

SSP) and six are made available for devices in the FPGA or RealView Logic Tile.

Note

The DMA controller cannot access the Tightly Coupled Memory in the ARM926EJ-S

core. Other access limitations are:

• The DMAC master 0 can always access the DMA APB and FPGA peripherals

• DMAC master 1 can always access dynamic and static memory.

• Accesses to other regions are usually mapped to AHB M2.

See AHB bridges and the bus matrix on page 3-10.

Table 4-32 DMAC implementation

Property Value

Location ARM926EJ-S PXP Development Chip

Memory base address

0x10130000

for DMAC (PL010)

0x10000064

for DMA mapping

0x10000068

for DMA mapping

0x1000006C

for DMA mapping

Interrupt 17 on the primary controller

DMA NA

Release version ARM DMAC PL080 r1p0

Reference documentation ARM PrimeCell DMA (PL080) Technical Reference Manual

(see also DMA on page 3-65)

1 2 ... 213 214 215 216 217 218 219 220 221 222 223 ... 401 402

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