ARM Cortex-M3 User Manual Page 21

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21
Interrupt Handling
One Non
-
Maskable Interrupt (INTNMI) supported
1
-
240 prioritizable interrupts supported
Interrupts can be masked
Implementation option selects number of interrupts supported
Nested Vectored Interrupt Controller (NVIC) is tightly coupled with processor core
Interrupt inputs are active HIGH
Cortex
-
M3
Processor Core
INTNMI
NVIC
Cortex
-
M3
1
-
240 Interrupts
INTISR[239:0]
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