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ARM Cortex-M3 User Manual Page 4
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4
ARM Cortex
-
M3 Processor
FPB
BKPT
A
RM
Cortex
-
M3
Core
ETM
Instruction
T
race
Bus
Matri
x
I
D
DA
P
JT
AG/SW
D
NVIC
1
-
240
Interrupts
8
-
256
Priorities
Code
Buses
to Flash
to Code SRAM
Sy
stem
Bus
to Stack SRAM
to Peripherals
DWT
Data
T
race
ITM
Instrumen
tation
T
race
TPIU
T
race
Port
Serial
-
Wire
Vie
wer
(1
-
pin)
(5
-
pins)
T
race
Port
MPU
1
2
3
4
5
6
7
8
9
...
40
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ARM Cortex
1
Introduction
1
M3 Processor
4
M3 Microcontroller
5
ARM and Thumb Performance
7
The Thumb
8
2 instruction set
8
M3 Register Set
10
Program Status Register
11
An Example AMBA System
12
Memory Map
13
Processor Privilege
16
Memory Protection Unit (MPU)
17
0x02000000
18
Word alias
19
Physical bit
19
Conditional Execution
20
Interrupt Handling
21
Exception Handling
22
Power Management
23
M3 Debug
24
M3 Datapath
26
M3 Pipeline
27
Optimal Pipelining
28
Branch Pipeline Example
29
LDR Pipeline Example
30
STR Pipeline Example
31
M3 Development Platforms
35
Rapid Prototyping
36
Documentation
39
University Resources
40
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