ARM ARM7TDMI User Manual download pdf (Page 149)

Instruction Cycle Timings

6.5 Data operations

A data operation executes in a single datapath cycle unless a shift is determined by the

contents of a register. A register is read onto the A bus, and a second register or the

immediate field onto the B bus (see Figure 1-3 on page 1-8). The ALU combines the A

bus source and the shifted B bus source according to the operation specified in the

instruction, and the result, when required, is written to the destination register.

Note

Compare and test operations do not produce results. Only the ALU status flags are

affected.

An instruction prefetch occurs at the same time as the data operation, and the program

counter is incremented.

When the shift length is specified by a register, an additional datapath cycle occurs

during this cycle. The data operation occurs on the next cycle which is an internal cycle

that does not access memory. This internal cycle can be merged with the following

sequential access by the memory manager as the address remains stable through both

cycles.

The PC can be one or more of the register operands. When it is the destination, external

bus activity can be affected. If the result is written to the PC, the contents of the

instruction pipeline are invalidated, and the address for the next instruction prefetch is

taken from the ALU rather than the address incrementer. The instruction pipeline is

refilled before any further execution takes place, and during this time exceptions are

ignored.

PSR transfer operations (MSR and MRS) exhibit the same timing characteristics as the

data operations except that the PC is never used as a source or destination register.

The cycle timings are listed in Table 6-4 on page 6-8 where:

• pc is the address of the branch instruction

• alu is the destination address calculated by the ARM7TDMI core

• (alu) is the contents of that address.

1 2 ... 144 145 146 147 148 149 150 151 152 153 154 ... 283 284

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ARM ARM7TDMI User Manual Page 149