ARM ARM7TDMI User Manual Page 65
- Page / 284
- Table of contents
- BOOKMARKS
Rated. / 5. Based on customer reviews
Programmer’s Model
ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-19
2.8.5 Interrupt request
The Interrupt Request (IRQ) exception is a normal interrupt caused by a LOW level on
the nIRQ input. IRQ has a lower priority than FIQ, and is masked on entry to an FIQ
sequence. As with the nFIQ input, nIRQ passes into the core through a synchronizer.
Irrespective of whether exception entry is from ARM state or Thumb state, an IRQ
handler returns from the interrupt by executing:
SUBS PC,R14_irq,#4
You can disable IRQ at any time, by setting the I bit in the CPSR from a privileged
mode.
2.8.6 Abort
An abort indicates that the current memory access cannot be completed. An abort is
signaled by the external ABORT input. The ARM7TDMI processor checks for the abort
exception at the end of memory access cycles.
The abort mechanism allows the implementation of a demand-paged virtual memory
system. In such a system, the processor is allowed to generate arbitrary addresses. When
the data at an address is unavailable, the Memory Management Unit (MMU) signals an
abort.
The abort handler must then:
• Work out the cause of the abort and make the requested data available.
• Load the instruction that caused the abort using an
LDR Rn,[R14_abt,#-8]
instruction to determine whether that instruction specifies base register
write-back. If it does, the abort handler must then:
— determine from the instruction what the offset applied to the base register
by the write-back was
— apply the opposite offset to the value that will be reloaded into the base
register when the abort handler returns.
This ensures that when the instruction is retried, the base register will have been
restored to the value it had when the instruction was originally executed.
The application program needs no knowledge of the amount of memory available to it,
nor is its state in any way affected by the abort.
There are two types of abort:
• a Prefetch Abort occurs during an instruction prefetch
• a Data Abort occurs during a data access.
- ARM7TDMI 1
- Contents 5
- Chapter 3 Memory Interface 6
- Chapter 5 Debug Interface 6
- Appendix A Signal Description 7
- Appendix B Debug in Depth 7
- List of Tables 10
- List of Figures 13
- • Further reading on page xxi 17
- • Feedback on page xxii 17
- About this document 18
- Preface 19
- Further reading 21
- Feedback 22
- Chapter 1 23
- Introduction 23
- 1.1 About the ARM7TDMI core 24
- 1.2 Architecture 27
- Figure 1-3 Main processor 30
- <Oprnd2> 32
- #32bit_Imm 32
- <reglist> 32
- [Rn, #+/-12bit_Offset] 37
- [Rn, +/-Rm] 37
- Register 37
- [Rn, #+/-8bit_Offset] 39
- [Rn, #+/-(8bit_Offset*4)] 39
- Operand 2 40
- Chapter 2 47
- Programmer’s Model 47
- 31 24 23 16 15 8 7 0 50
- Word at address A 50
- 2.4 Data types 52
- 2.5 Operating modes 53
- 2.6 Registers 54
- MOV PC, R14 62
- MOVS PC, R14_svc 62
- MOVS PC, R14_und 62
- SUBS PC, R14_abt, #4 62
- SUBS PC, R14_fiq, #4 63
- SUBS PC, R14_irq, #4 63
- SUBS PC, R14_abt, #8 63
- SUBS PC,R14_fiq,#4 64
- SUBS PC,R14_irq,#4 65
- LDR Rn,[R14_abt,#-8] 65
- SUBS PC,R14_abt,#4 66
- SUBS PC,R14_abt,#8 66
- 0x00000004 67
- 0x00000008 67
- 0x0000000C 67
- 0x00000010 68
- 0x00000014 68
- 0x00000018 68
- 0x0000001C 68
- 2.9 Interrupt latencies 69
- 2.10 Reset 70
- Chapter 3 71
- 3.2 Bus interface signals 73
- 3.3 Bus cycle types 74
- Figure 3-4 Internal cycles 78
- Figure 3-5 Merged IS cycle 79
- 3.4 Addressing signals 81
- Table 3-5 nTRANS encoding 83
- 1 Privileged 83
- 3.5 Address timing 84
- 3.6 Data timed signals 87
- DOUT[31:0] 89
- XDATA[31:0] 89
- DIN[31:0] 89
- Figure 3-18 Memory access 95
- Figure 3-20 Data replication 98
- 3.7 Stretching access times 99
- Memory Interface 100
- 3.9 Privileged mode access 102
- Figure 3-22 Reset sequence 103
- Chapter 4 105
- Coprocessor Interface 105
- 4.1 About coprocessors 106
- Signal Direction Meaning 110
- Table 4-2 Handshaking signals 110
- ARM core 116
- Coprocessor 116
- 4.7 Undefined instructions 120
- 4.8 Privileged instructions 121
- Chapter 5 123
- Debug Interface 123
- 5.1 About the debug interface 124
- EmbeddedICE 127
- Main processor 127
- TAP controller 127
- 5.3 Debug interface signals 128
- Figure 5-3 Debug state entry 129
- MOV PC, #0 133
- 5.7 Disabling EmbeddedICE 137
- MRC CP14, 0, Rd, C0, C0, 0 139
- MCR CP14, 0, Rn, C1, C0, 0 139
- MRC CP14, 0, Rd, C1, C0, 0 139
- Chapter 6 143
- Instruction Cycle Timings 143
- SUB PC,R14,#4 to MOV PC,R14 146
- 6.3 Thumb branch with link 147
- 6.4 Branch and Exchange 148
- 6.5 Data operations 149
- Thumb state 150
- 6.7 Load register 154
- 6.8 Store register 156
- 6.9 Load multiple registers 157
- 6.10 Store multiple registers 159
- 6.11 Data swap 160
- 6.19 Unexecuted instructions 170
- Chapter 7 173
- AC and DC Parameters 173
- Figure 7-1 General timing 176
- 7.7 Output 3-state timing 182
- 7.10 Configuration pin timing 185
- 7.16 Breakpoint timing 192
- TCK to ECLK delay Maximum 193
- 7.20 Reset period timing 196
- In Table 7-23: 200
- 7.25 DC parameters 206
- Appendix A 207
- Signal Description 207
- A.1 Signal description 208
- A.1.3 Signals 209
- Appendix B 219
- Debug in Depth 219
- Scan chain 2 222
- B.1.2 TAP state machine 223
- B.3 Pullup resistors 225
- B.4 Instruction register 226
- B.5 Public instructions 227
- B.6 Test data registers 232
- Figure B-4 Input scan cell 235
- B.7 The ARM7TDMI core clocks 240
- Internal cycles 246
- 0 E0802000; ADD R2, R0, R0 247
- 1 E1826001; ORR R6, R2, R1 247
- MOV R0, R0 247
- SUB PC, PC, #28 247
- 0 E1A00000; MOV R0, R0 248
- 1 E1A00000; MOV R0, R0 248
- 0 EAFFFFF0; B -16 248
- 0 EAFFFFFA; B -6 249
- - (4+N+3S) 249
- - (3+N+3S) 249
- B.11 Scan chain cell data 251
- B.11.2 Scan chain 1 cells 255
- 31 D[30] Input/output 257
- 32 D[31] Input/output 257
- 33 BREAKPT Input 257
- Number Signal Type 257
- B.12 The watchpoint registers 258
- 0xFFFFFFFF 260
- B.13 Programming breakpoints 263
- 0xDEEEDEEE 264
- 0x00000000 264
- B.14 Programming watchpoints 265
- INTDIS DBGRQ DBGACK 266
- B.18 EmbeddedICE timing 272
- B.19 Programming Restriction 273
- Glossary 275
Related products and manuals for Processors ARM ARM7TDMI
Processors ARM Cortex-M3 User Manual
(41 pages)
(41 pages)
Processors ARM ARM7TDMI User Manual
(18 pages)
(18 pages)
Processors ARM ARM926EJ-S Specifications
(332 pages)
(332 pages)
Processors ARM ARM926EJ-S User's Guide
(402 pages)
(402 pages)
Processors ARM ARM7TDMI Datasheet
(42 pages)
(42 pages)
Processors ARM ARM7TDMI User Manual
(242 pages)
(242 pages)
Processors ARM ARM7TDMI User Manual
(43 pages)
(43 pages)
© 2020, manymanuals.com. All rights reserved. | 0.881 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comments to this Manuals