ARM ARM7TDMI User Manual download pdf (Page 240)

Debug in Depth

B.7 The ARM7TDMI core clocks

The ARM7TDMI core has two clocks:

• the memory clock, MCLK

• an internally TCK generated clock, DCLK.

During normal operation, the core is clocked by MCLK and internal logic holds DCLK

LOW. When the ARM7TDMI core is in the debug state, the core is clocked by DCLK

under control of the TAP state machine and MCLK can free-run. The selected clock is

output on the signal ECLK for use by the external system.

Note

When the CPU core is being debugged and is running from DCLK, nWAIT has no

effect.

B.7.1 Clock switch during debug

When the ARM7TDMI core enters debug state, it must switch from MCLK to DCLK.

This is handled automatically by logic in the ARM7TDMI core. On entry to debug state,

the core asserts DBGACK in the HIGH phase of MCLK. The switch between the two

clocks occurs on the next falling edge of MCLK. This is shown in Figure B-5.

Figure B-5 Clock switching on entry to debug state

The ARM7TDMI core is forced to use DCLK as the primary clock until debugging is

complete. On exit from debug, the core must be enabled to synchronize back to MCLK.

This must be done in the following sequence:

1. The final instruction of the debug sequence must be shifted into the data bus scan

chain and clocked in by asserting DCLK.

Multiplexer

switching point

MCLK

DBGACK

DCLK

ECLK

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ARM ARM7TDMI User Manual Page 240