ARM ARM7TDMI User Manual Page 159
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Instruction Cycle Timings
ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-17
6.10 Store multiple registers
The store multiple instruction proceeds very much as load multiple instruction, without
the final cycle. The abort handling is much more straightforward as there is no
wholesale overwriting of registers.
The cycle timings are listed in Table 6-13 where:
• Ra is the first register specified
• R• are the subsequent registers specified.
Table 6-13 Store multiple registers instruction cycle operations
Register Cycle Address MAS[1:0] nRW Data nMREQ SEQ nOPC
Single register 1 pc+2L i 0 (pc+2L) 0 0 0
2alu 2 1Ra0 01
pc+3L
n registers (n>1) 1 pc+8 i 0 (pc+2L) 0 0 0
2alu 2 1Ra0 11
• alu+• 21R• 011
nalu+• 21R• 011
n+1 alu+• 21R• 001
pc+12
- ARM7TDMI 1
- Contents 5
- Chapter 3 Memory Interface 6
- Chapter 5 Debug Interface 6
- Appendix A Signal Description 7
- Appendix B Debug in Depth 7
- List of Tables 10
- List of Figures 13
- • Further reading on page xxi 17
- • Feedback on page xxii 17
- About this document 18
- Preface 19
- Further reading 21
- Feedback 22
- Chapter 1 23
- Introduction 23
- 1.1 About the ARM7TDMI core 24
- 1.2 Architecture 27
- Figure 1-3 Main processor 30
- <Oprnd2> 32
- #32bit_Imm 32
- <reglist> 32
- [Rn, #+/-12bit_Offset] 37
- [Rn, +/-Rm] 37
- Register 37
- [Rn, #+/-8bit_Offset] 39
- [Rn, #+/-(8bit_Offset*4)] 39
- Operand 2 40
- Chapter 2 47
- Programmer’s Model 47
- 31 24 23 16 15 8 7 0 50
- Word at address A 50
- 2.4 Data types 52
- 2.5 Operating modes 53
- 2.6 Registers 54
- MOV PC, R14 62
- MOVS PC, R14_svc 62
- MOVS PC, R14_und 62
- SUBS PC, R14_abt, #4 62
- SUBS PC, R14_fiq, #4 63
- SUBS PC, R14_irq, #4 63
- SUBS PC, R14_abt, #8 63
- SUBS PC,R14_fiq,#4 64
- SUBS PC,R14_irq,#4 65
- LDR Rn,[R14_abt,#-8] 65
- SUBS PC,R14_abt,#4 66
- SUBS PC,R14_abt,#8 66
- 0x00000004 67
- 0x00000008 67
- 0x0000000C 67
- 0x00000010 68
- 0x00000014 68
- 0x00000018 68
- 0x0000001C 68
- 2.9 Interrupt latencies 69
- 2.10 Reset 70
- Chapter 3 71
- 3.2 Bus interface signals 73
- 3.3 Bus cycle types 74
- Figure 3-4 Internal cycles 78
- Figure 3-5 Merged IS cycle 79
- 3.4 Addressing signals 81
- Table 3-5 nTRANS encoding 83
- 1 Privileged 83
- 3.5 Address timing 84
- 3.6 Data timed signals 87
- DOUT[31:0] 89
- XDATA[31:0] 89
- DIN[31:0] 89
- Figure 3-18 Memory access 95
- Figure 3-20 Data replication 98
- 3.7 Stretching access times 99
- Memory Interface 100
- 3.9 Privileged mode access 102
- Figure 3-22 Reset sequence 103
- Chapter 4 105
- Coprocessor Interface 105
- 4.1 About coprocessors 106
- Signal Direction Meaning 110
- Table 4-2 Handshaking signals 110
- ARM core 116
- Coprocessor 116
- 4.7 Undefined instructions 120
- 4.8 Privileged instructions 121
- Chapter 5 123
- Debug Interface 123
- 5.1 About the debug interface 124
- EmbeddedICE 127
- Main processor 127
- TAP controller 127
- 5.3 Debug interface signals 128
- Figure 5-3 Debug state entry 129
- MOV PC, #0 133
- 5.7 Disabling EmbeddedICE 137
- MRC CP14, 0, Rd, C0, C0, 0 139
- MCR CP14, 0, Rn, C1, C0, 0 139
- MRC CP14, 0, Rd, C1, C0, 0 139
- Chapter 6 143
- Instruction Cycle Timings 143
- SUB PC,R14,#4 to MOV PC,R14 146
- 6.3 Thumb branch with link 147
- 6.4 Branch and Exchange 148
- 6.5 Data operations 149
- Thumb state 150
- 6.7 Load register 154
- 6.8 Store register 156
- 6.9 Load multiple registers 157
- 6.10 Store multiple registers 159
- 6.11 Data swap 160
- 6.19 Unexecuted instructions 170
- Chapter 7 173
- AC and DC Parameters 173
- Figure 7-1 General timing 176
- 7.7 Output 3-state timing 182
- 7.10 Configuration pin timing 185
- 7.16 Breakpoint timing 192
- TCK to ECLK delay Maximum 193
- 7.20 Reset period timing 196
- In Table 7-23: 200
- 7.25 DC parameters 206
- Appendix A 207
- Signal Description 207
- A.1 Signal description 208
- A.1.3 Signals 209
- Appendix B 219
- Debug in Depth 219
- Scan chain 2 222
- B.1.2 TAP state machine 223
- B.3 Pullup resistors 225
- B.4 Instruction register 226
- B.5 Public instructions 227
- B.6 Test data registers 232
- Figure B-4 Input scan cell 235
- B.7 The ARM7TDMI core clocks 240
- Internal cycles 246
- 0 E0802000; ADD R2, R0, R0 247
- 1 E1826001; ORR R6, R2, R1 247
- MOV R0, R0 247
- SUB PC, PC, #28 247
- 0 E1A00000; MOV R0, R0 248
- 1 E1A00000; MOV R0, R0 248
- 0 EAFFFFF0; B -16 248
- 0 EAFFFFFA; B -6 249
- - (4+N+3S) 249
- - (3+N+3S) 249
- B.11 Scan chain cell data 251
- B.11.2 Scan chain 1 cells 255
- 31 D[30] Input/output 257
- 32 D[31] Input/output 257
- 33 BREAKPT Input 257
- Number Signal Type 257
- B.12 The watchpoint registers 258
- 0xFFFFFFFF 260
- B.13 Programming breakpoints 263
- 0xDEEEDEEE 264
- 0x00000000 264
- B.14 Programming watchpoints 265
- INTDIS DBGRQ DBGACK 266
- B.18 EmbeddedICE timing 272
- B.19 Programming Restriction 273
- Glossary 275
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