ARM ARM7TDMI User Manual download pdf (Page 23)

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The instructions below demonstrate a push operation followed by a pop operation

assuming an empty-ascending stack. Note that by including the link register (R14) in

the push operation, and the PC in the pop operation, a subroutine will return to the

caller as part of the context save/restore.

STMEA R13!, {R0, R2-R3, LR} ;memory[R13]  R0

;memory[R13+4]  R2

;memory[R13+8]  R3

;memory[R13+12]  R14

;R13  R13 + 16

LDMEA R13!, {R0, R2-R4, PC} ;R0  memory[R13-16]

;R2  memory[R13-12]

;R3  memory[R13-8]

;PC  memory[R13-4]

;R13  R13 - 16

4.12 LDR – Load Register

Syntax:

LDR{<cond>} <Rd>, <addressing_mode>

RTL:

if(cond)

Rd  memory[memory_address]

if(writeback)

Rn  end_address

Flags updated:

None

Encoding:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cond 0 1 I P U 0 W 1 Rn Rd addressing_mode

Usage and Examples:

The LDR instruction reads a word from memory and writes it to the destination register.

See the section

Load/Store Register Addressing Modes

for a description of the available

addressing modes.

LDR R0, [R1] ;R0 = memory[R1]

If the memory address is not word-aligned, the value read is rotated right by 8 times

the value of bits [1:0] of the memory address. If R15 is specified as the destination, the

value is loaded from memory and written to the PC, effecting a branch.

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 42 43

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ARM ARM7TDMI User Manual Page 23