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4.22 MVN – Move Negative

Syntax:

MVN{<cond>}{S} <Rd>, <shifter_operand>

RTL:

if(cond)

Rd  NOT shifter_operand

if(S==1 and Rd==R15)

CPSR  SPSR

Flags updated if S used and Rd is not R15 (PC):

N, Z, C

Encoding:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cond 0 0 I 1 1 1 1 S SBZ Rd shifter operand

Usage and Examples:

MVN complements the value of a register or an immediate value and stores it in the

destination register.

MVN R1, R0, LSL #2 ;R1 <- NOT (R0 * 4)

MVN R1, #1 ;R1 <- 0xFFFFFFFE

If the S bit is set and the destination is R15 (the PC), the SPSR is also copied to CPSR.

This form of the instruction used to return from an exception mode.

4.23 ORR – Bit-wise Inclusive-OR

Syntax:

ORR{<cond>}{S} <Rd>, <Rn>, <shifter_operand>

RTL:

if(cond)

Rd  Rn OR shifter_operand

Flags updated if S used:

N, Z, C

Encoding:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cond 0 0 I 1 1 0 0 S Rn Rd shifter operand

Usage and Examples:

OR R0, R0, #0x8000 ;sets bit D15 of R0

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 42 43

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ARM ARM7TDMI User Manual Page 29