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4.28 SMULL – Signed Multiply Long

Syntax:

SMULL{<cond>}{S} <Rd_LSW>, <Rd_MSW>, <Rm>, <Rs>

RTL:

if(cond)

Rd_MSW:Rd_LSW  Rs • Rm

Flags updated if S used:

N, Z (V, C are unpredictable)

Encoding:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cond 0 0 0 0 1 1 0 S Rd_MSW Rd_LSW Rs 1 0 0 1 Rm

Usage and Examples:

SMULL performs a signed 32x32 multiply operation. The product of Rm and Rs is stored

as a 64-bit signed value in the register pair Rd_MSW:Rd_LSW. All values are interpreted

as 2’s-complement.

The instruction below stores the product of R2 and R3 as a 64-bit number in R1:0.

SMULL R0, R1, R2, R3

4.29 STM – Store Multiple

There are two distinct variants of the STM instruction. One of them is for use in

conjunction with exception processing, and is not described here. Further information

can be obtained in the ARM Architecture Reference Manual.

Syntax:

STM{<cond>}<addressing_mode>, <Rn>{!}, <registers>

RTL:

if(cond)

start_address  Rn

for i = 0 to 15

if(register_list[i] == 1)

memory[next_address]  Ri

if(writeback)

Rn  end_address

Flags updated:

None

Encoding:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cond 1 0 0 P U 0 W 0 Rn register_list

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 42 43

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ARM ARM7TDMI User Manual Page 32