ARM ARM7TDMI User Manual download pdf (Page 7)

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3 Addressing, Operands and Directives

3.1 General Notes

In general, using R15 (PC) as the destination register is not appropriate for most

instructions. Many instructions will have unpredictable behavior if R15 is the destination.

The ARM supports instruction set extensions by reserving certain bit combinations in

the operand fields of otherwise valid instructions. The assembler will ensure that these

bit combinations are not used, but these must be avoided when hand-coding

instructions.

The notation SBZ means “should be zeros”, SBO means “should be ones”.

3.2 Shifter Operands

The shifter operand is represented by the least-significant 12 bits of the instruction. It

can take one of eleven forms, as listed below. For illustration, each form has one or

more examples based on the Compare instruction (CMP <Rn>, <shifter_operand>). For

instructions that use shifter operands, the C flag update is dependent on the form of

the operand used.

3.2.1 Immediate Operands

Immediate values are signified by a leading # symbol. The operand is actually stored in

the instruction as an 8-bit value with a 4-bit rotation code. The resultant value is the 8-

bit value rotated right 0-30 bits (twice the rotation code amount), as illustrated below.

Only values that can be represented in this form can be encoded as immediate

operands.

The assembler will make substitutions of comparable instructions if it makes it possible

to create the desired immediate operand. For example, CMP R0, #-1 is not a legal

instruction since it is not possible to specify -1 (0xFFFFFFFF) as an immediate value, but

it can be replaced by CMN R0, #1. If the rotate value is non-zero, the C flag is set to bit

31 of the immediate value, otherwise it is unchanged.

Syntax: #<immediate>

Example: CMP R0, #7

Encoding:

11 10 9 8 7 6 5 4 3 2 1 0

rotate_imm immediate_8

1 2 3 4 5 6 7 8 9 10 11 12 ... 42 43

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ARM ARM7TDMI User Manual Page 7