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5.4 LDR – Load Register

Syntax:

LDR{cond} <Rd>, =<expression>

LDR{cond} <Rd>, =<label-expression>

Description:

The LDR pseudo-instruction will generate an instruction to load the destination register

with the desired value.

The <expression> field must evaluate to a numeric constant. If the constant is an

allowable immediate expression (or the complement of one), a MOV or MVN instruction

will be generated. If it is not, the assembler will place the value in a memory location,

and generate a PC-relative load instruction to load it from that memory location.

If a label is specified, the assembler will generate a local memory location to store the

label address, and include the appropriate linker directives so that the correct address

will be in that location after linking.

5.5 LSL – Logical Shift Left

Syntax:

LSL{cond}{S} <Rd>, <Rm>, <Rs>

LSL{cond}{S} <Rd>, <Rm>, <#shift_count>

Description:

LSL is a synonym for the MOV instruction with an LSL shifter operand. If an immediate

shift count is used, it is limited to the range 0-31. If Rm is not included, the assembler

will assume it is the same as Rd.

LSL R0, R1 is equivalent to MOV R0, R0, LSL R1

LSL R0, R1, R2 is equivalent to MOV R0, R1, LSL R2

5.6 LSR – Logical Shift Right

Syntax:

LSR{cond}{S} <Rd>, <Rm>, <Rs>

LSR{cond}{S} <Rd>, <Rm>, <#shift_count>

Description:

LSR is a synonym for the MOV instruction with an LSR shifter operand. If an immediate

shift count is used, it is limited to the range 1-32. If Rm is not included, the assembler

will assume it is the same as Rd.

LSR R0, R1 is equivalent to MOV R0, R0, LSR R1

LSR R0, R1, R2 is equivalent to MOV R0, R1, LSR R2

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ARM ARM7TDMI User Manual Page 41