ARM ARM7TDMI User Manual Page 6

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1.2 ARM7TDMI – THUMB Instructions
The ARM7TDMI uses a fixed-length, 16-bit instruction encoding scheme for all Thumb
instructions. The Thumb instruction set is a subset of the ARM instruction set, and is intended to
permit a higher code density (smaller memory requirement) than the ARM instruction set in
many applications. The processor executes in Thumb mode when bit 5 of the CPSR is 1.
Exception processing is always done in ARM mode; the processor automatically switches to
ARM mode when entering an exception mode. Use of the Thumb instruction set will not be
required in ECE 353/315, and so is not covered here.
2 Conditional Execution
2.1 Condition Field
All ARM7TDMI instructions can be executed conditionally, based on a 4-bit condition field in
the instruction. The processor tests the state of the condition flags in the CPSR (N, Z, V, C), and
if the condition flag state matches the condition, the instruction executes normally. If the
condition flag state does not match the condition, the instruction is executed as a NOP (no
operation).
2.2 Condition Codes
The condition codes and use are shown below. If the condition is omitted in instructions, the AL
(always) condition is used to specify that the instruction should always execute.
Opcode
[31:28]
Mnemonic
Extension
Meaning
Condition flag state
0000 EQ Equal Z==1
0001 NE Not equal Z==0
0010 CS/HS Carry set / unsigned higher or same C==1
0011 CC/LO Carry clear / unsigned lower C==0
0100 MI Minus / negative N==1
0101 PL Plus / positive or zero N==0
0110 VS Overflow V==1
0111 VC No overflow V==0
1000 HI Unsigned higher (C==1) AND (Z==0)
1001 LS Unsigned lower or same (C==0) OR (Z==1)
1010 GE Signed greater than or equal N == V
1011 LT Signed less than N != V
1100 GT Signed greater than (Z==0) AND (N==V)
1101 LE Signed less than or equal (Z==1) OR (N!=V)
1110 AL Always (unconditional) Not applicable
1111 (NV) Never Obsolete, unpredictable in ARM7TDMI
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