ARM ARM926EJ-S Specifications download pdf (Page 13)

List of Figures

ARM926EJ-S Development Chip Reference

Manual

Figure 1-1 Typical application ..................................................................................................... 1-2

Figure 1-2 ARM926EJ-S Development Chip block diagram ....................................................... 1-3

Figure 1-3 Default system bus memory map for ARM DATA AHB bus .................................... 1-12

Figure 2-1 Enable signal generation for the Timer and Watchdog modules .............................. 2-5

Figure 2-2 Reference frequency select for Watchdog and Timer modules clock enable ........... 2-6

Figure 2-3 System mode control state machine ......................................................................... 2-8

Figure 2-4 Clock and reset block diagram ................................................................................ 2-13

Figure 2-5 External clock signals and clock selection .............................................................. 2-14

Figure 2-6 Power-on configuration block diagram .................................................................... 2-24

Figure 2-7 JTAG Test Access Port ........................................................................................... 2-26

Figure 2-8 Multi-ICE synchronization ....................................................................................... 2-27

Figure 3-1 Bus matrix configuration ............................................................................................ 3-4

Figure 3-2 AHB M1 interface ...................................................................................................... 3-7

Figure 3-3 AHB M2 interface ...................................................................................................... 3-8

Figure 3-4 AHB S interface ....................................................................................................... 3-13

Figure 3-5 Memory control signals ........................................................................................... 3-16

Figure 3-6 Default AHB memory map with SMC ...................................................................... 3-18

Figure 3-7 AHB memory map without SMC ............................................................................. 3-19

Figure 3-8 AHB M1 access determined by address range ....................................................... 3-20

Figure 3-9 AHB M1 access determined by ARM D .................................................................. 3-21

Figure 3-10 Default AHB memory map with no bridge remap and SMC .................................... 3-22

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ARM ARM926EJ-S Specifications Page 13