ARM ARM926EJ-S Specifications download pdf (Page 271)

Vectored Interrupt Controller (VIC)

17.2.6 Vectored interrupts

A vectored interrupt is only generated if the following are true:

• it is enabled in the interrupt enable register, VICIntEnable

• it is set to generate an IRQ interrupt in the interrupt select register, VICIntSelect

• it is enabled in the relevant vector control register,

VICVectCntl0-VICVectCntl15].

This prevents multiple interrupts being generated from a single interrupt request if the

controller is incorrectly programmed.

17.2.7 Software interrupts

The software can control the source interrupt lines to generate software interrupts.

These interrupts are generated before interrupt masking, in the same way as external

source interrupts. Software interrupts are cleared by writing to the software interrupt

clear register, VICSoftIntClear (see Interrupt control registers). This is normally done

at the end of the interrupt service routine.

17.2.8 Interrupt control registers

The base address of the PrimeCell VIC is

0x10140000

Note

To ensure that the vector address register can be read in a single instruction, the

PrimeCell VIC base address must be

0xFFFFF000,

the upper 4K of memory. Placing the

PrimeCell VIC anywhere else in memory increases interrupt latency as the ARM

processor is unable to access the VICVectorAddr register using a single instruction.

Use the MMU in the ARM926EJ-S to cause the VIC to appear at

0xFFFFF000

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ARM ARM926EJ-S Specifications Page 271