ARM ARM926EJ-S Specifications Page 244
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Synchronous Serial Port (SSP)
14-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
14.2 Functional description
This section describes the function of the SSP controller.
For detailed information on the internal organization and the SSP registers, see the ARM
PrimeCell Synchronous Serial Port Controller (PL022) Technical Reference Manual.
14.2.1 Using an external reference clock
In the slave mode of operation, the SSPCLKIN signal from the external master is
double synchronized and then delayed to detect an edge. It takes three SSPCLKs to
detect an edge on SSPCLKIN. SSPTXD has less setup time to the falling edge of
SSPCLKIN on which the master is sampling the line. The setup and hold times on
SSPRXD with reference to SSPCLKIN must be more conservative to ensure that it is
at the right value when the actual sampling occurs within the SSPMS. To ensure correct
device operation, SSPCLK must be at least 12 times faster than the maximum expected
frequency of SSPCLKIN.
The frequency selected for SSPCLK must accommodate the desired range of bit clock
rates. The ratio of minimum SSPCLK frequency to SSPCLKOUT maximum
frequency in the case of the slave mode is 12 and for the master mode it is two.
To generate a maximum bit rate of 1.8432Mbps in the Master mode, the frequency of
SSPCLK must be at least 3.6864MHz. With an SSPCLK frequency of 3.6864MHz, the
SSPCPSR register has to be programmed with a value of two and the SCR[7:0] field in
the SSPCR0 register must be programmed as zero.
To work with a maximum bit rate of 1.8432Mbps in the slave mode, the frequency of
SSPCLK must be at least 22.12MHz. With an SSPCLK frequency of 22.12MHz, the
SSPCPSR register can be programmed with a value of 12 and the SCR[7:0] field in the
SSPCR0 register can be programmed as zero. Similarly the ratio of SSPCLK maximum
frequency to SSPCLKOUT minimum frequency is 254x256.
The minimum frequency of SSPCLK is governed by the following equations, both of
which have to be satisfied:
F
SSPCLK
(min) => 2 x F
SSPCLKOUT
(max) [for master mode]
F
SSPCLK
(min) => 12 x F
SSPCLKIN
(max) [for slave mode].
The maximum frequency of SSPCLK is governed by the following equations, both of
which have to be satisfied:
F
SSPCLK
(max) <= 254 x 256 x F
SSPCLKOUT
(min) [for master mode]
F
SSPCLK
(max) <= 254 x 256 x F
SSPCLKIN
(min) [for slave mode]
- ARM926EJ-S Development Chip 1
- CE Declaration of Conformity 3
- Contents 5
- List of Tables 10
- List of Figures 13
- • Feedback on page xxiii 17
- About this document 18
- Preface 19
- Feedback 23
- Chapter 1 27
- Introduction 27
- Platform 28
- ARM926EJ-S PXP 29
- Subsystem 29
- 1.2 Functional description 30
- 1.3 External interfaces 35
- 0x00000000 37
- 0x70000000 37
- 0x20000000 37
- 0x30000000 37
- ARM D bus 38
- Chapter 2 41
- 0x101E0000 42
- 2.2 Clock control 53
- Figure 2-5 54
- 2.4 JTAG logic 65
- Chapter 3 75
- $50(-6'HY&KLS 81
- 2IIFKLS$+%EULGJH 81
- %XVPDWUL[ 82
- 1xxx x00 84
- 0 001-111 x 01 84
- 0000 010 84
- 0000 111 84
- +5($'<6,1 87
- +5($'<2876287 87
- 3.2 Memory map options 89
- Configuration 90
- PWP System 90
- Controller 90
- 0x80000000 94
- 0x03FFFFFF 99
- • REMAPSTATIC HIGH 101
- 3.2.6 APB address maps 103
- 3.2.7 MBX memory map 105
- Figure 3-20 105
- 3.3 AHB signals to pads 106
- Controllers and Peripherals 109
- AHB Monitor 111
- Chapter 4 111
- 4.1 About the AHB monitor 112
- 4.2 Functional description 113
- 89181922232829 332 114
- 0x101D0000 121
- 4.3 AHB Monitor registers 133
- CtArmdBurstIncr8 142
- CtDma0BurstIncr8 142
- CtDma1BurstIncr8 142
- CtClcdBurstIncr8 142
- CtExpBurstIncr8 142
- CtGxiRdAddrWait 147
- CtGxiRdDataWait 147
- 4.3.33 AHBMONPeriphID 0 to 3 150
- 4.3.34 AHBMONPCellID 151
- It is set at the value of 151
- Chapter 5 153
- Color LCD Controller (CLCDC) 153
- 5.1 About the CLCDC 154
- 5.2 Functional description 156
- ARM926EJ-S Dev. Chip 157
- 32 32 2 2 64 160
- 64 64 2 4 256 160
- ClcdCrsrXY(X) 161
- ClcdCrsrXY(Y) 161
- 0x10120800 163
- Cursor0 164
- Undefined 170
- 31 6543 10 170
- CrsrNumber[1:0] 170
- CrsrFrameSync 172
- CrsrSize 172
- CrsrY Undefined CrsrX 173
- 31 14 13 8 7 6 5 0 174
- CrsrClipY CrsrClipX 174
- 0xFE0-0xFEC 179
- 0xFF0-0xFFC 181
- 5.4 CLCD signals on pads 183
- Chapter 6 185
- MOVE Coprocessor 185
- Figure 6-1 MOVE overview 187
- Chapter 7 189
- MBX HR-S Graphics Accelerator 189
- 0x40000000 190
- 7.2 Memory map and registers 194
- Translation table in 196
- Static registers 196
- Chapter 8 197
- 0x10130000 198
- 8.2 Functional description 200
- 8.3 DMA signals on pads 203
- Chapter 9 205
- 0x101E4000 206
- 0x101E5000 206
- 0x101E6000 206
- 0x101E7000 206
- 9.2 Functional description 207
- 9.3 GPIO signals on pads 209
- Chapter 10 211
- 0x10110000 212
- 10.3 MPMC signals on pads 218
- Chapter 11 221
- Real-Time Clock (RTC) 221
- 0xFFFFFFFF 222
- 11.2 Functional description 223
- Chapter 12 225
- Smart Card Interface (SCI) 225
- 12.1 About the ARM SCI 226
- 12.2 Functional description 228
- 12.3 SCI signals on pads 230
- Chapter 13 231
- 0x10100000 232
- 13.2 Functional description 235
- ARM926EJ-S 235
- Dev. Chip 235
- GX175 MPMC 236
- PL093 SSMC 236
- Multiplex 236
- 13.2.1 Implementation details 238
- 13.3 SSMC signals on pads 239
- Chapter 14 241
- Synchronous Serial Port (SSP) 241
- 0x101F4000 242
- 14.2 Functional description 244
- 14.3 SSP signals on pads 246
- Chapter 15 247
- Dual Timer/Counters 247
- 0x101E2000 248
- 0x101E3000 248
- 15.2 Functional description 249
- AMBA APB 250
- Interface 250
- Clock control 250
- Chapter 16 253
- UART Controller 253
- 0x101F1000 254
- 0x101F2000 254
- 0x101F3000 254
- 16.2 Functional description 256
- 16.3 UART signals on pads 260
- Chapter 17 263
- 0x10140000 264
- 17.2 Functional description 266
- 0xFFFFF000 271
- 17.2.9 Implementation details 272
- 17.3 VIC signals on pads 273
- Chapter 18 275
- 18.4 Modes of operation 280
- Chapter 19 283
- Watchdog Timer 283
- 0x101E1000 284
- 19.2 Functional description 285
- 0x101E1018 286
- 0x101E1BFC 286
- 0x101E1F08 286
- 0x101E1FDC 286
- Appendix A 287
- Signals on Pads 287
- A.1 Pad signals by function 288
- Appendix B 319
- B.1 Mechanical details 320
- B.2 Electrical specification 321
- Table B-3 Power estimate 322
- Description Power 322
- Total I/O Power 3.5W 322
- Total 4.5 W 322
- Appendix C 323
- Timing Specification 323
- Reference clock 324
- Output signals from 324
- Input signals to 324
- C.2 AHB bus timing 325
- C.3 Memory timing 326
- C.4 Peripheral timing 327
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