ARM ARM926EJ-S Specifications download pdf (Page 238)

Synchronous Static Memory Controller (SSMC)

13.2.1 Implementation details

Table 13-1 describes the internal signals that are configurable or tied off.

Table 13-1 Internal signal descriptions

Signal name Type

Source/

destination

Description

SMBIGENDIAN Input Configuration

control

This static configuration bit indicates the type of endianness of

the memory system:

0 = little-endian

1 = big-endian.

SMBUSBACKOFFEBI Input LOW Release bus signal, tells SSMC to release bus. Only used when

EXTBUSMUX is tied to one.

SMBUSGNTEBI Input LOW Bus grant signal, indicates that the SSMC is granted control of

the external bus. Only used when EXTBUSMUX is tied to

one.

SMBUSREQEBI Output Not used Bus request signal, indicates that the SSMC has requested use

of the external bus. Only used when EXTBUSMUX is tied to

one.

SMEXTBUSMUX Input LOW This static configuration bit indicates if the internal bus

multiplexor (DBI) is used, or if an external bus multiplexor

(for example EBI) is used instead:

0 = internal bus multiplexor 1 = external bus multiplexor

SMMEMCLK Input Configuration

control

Memory clock.

SMMEMCLKRATIO[1:0

]

Input Configuration

control

Defines ratio of SMMEMCLK to HCLK:

00 - SMMEMCLK = HCLK

01 - SMMEMCLK = HCLK/2

10 - SMMEMCLK = HCLK/3

11 - Reserved

nSMBURSTWAIT[7:1] Input HIGH Synchronous burst wait input used by the external device to

delay a synchronous burst transfer.

SMCS[7:0] Output Not used Active HIGH chip selects.

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ARM ARM926EJ-S Specifications Page 238