ARM ARM926EJ-S Specifications download pdf (Page 280)

ARM Vector Floating Point Coprocessor (VFP9)

18.4 Modes of operation

The VFP9-S coprocessor provides full IEEE 754 standard compatibility through a

combination of hardware and software. There are rare cases that require significant

additional compute time to resolve correctly according to the requirements of the IEEE

754 standard. For instance, the VFP9-S coprocessor does not process subnormal input

values directly. To provide correct handling of subnormal inputs according to the IEEE

754 standard, a trap is made to support code to process the operation. Using the support

code for processing this operation can require hundreds of cycles. In some applications

this is unavoidable, because compliance with the IEEE 754 standard is essential to

proper operation of the program. In many other applications, especially in the

embedded market, strict compliance to the IEEE 754 standard is unnecessary, while

determinable runtime, low interrupt latency, and low power are of more importance.

The following sections describe the two VFP9-S coprocessor modes of operation:

• Full-compliance mode

• Flush-to-Zero mode on page 18-7

• Default NaN mode on page 18-7

• RunFast Mode on page 18-8.

18.4.1 Full-compliance mode

When the VFP9-S coprocessor is in Full-compliance mode, all operations that cannot

be processed according to the IEEE 754 standard use support code for assistance. The

operations requiring support code are:

• Any CDP operation involving a subnormal input when not in Flush-to-Zero

mode. Enable Flush-to-Zero mode by setting the FZ bit, FPSCR[24].

• Any CDP operation involving a NaN input when not in Default NaN mode.

Enable Default NaN mode by setting the DN bit, FPSCR[25].

• Any CDP operation that has the potential of generating an underflow condition

when not in Flush-to-Zero mode.

• Any CDP operation when Inexact exceptions are enabled. Enable Inexact

exceptions by setting the IXE bit, FPSCR[12].

• Any CDP operation that can cause an overflow while Overflow exceptions are

enabled. Enable Overflow exceptions by setting the OFE bit, FPSCR[10].

• Any CDP operation that involves an invalid combination as the result of a product

overflow when Invalid Operation exceptions are enabled. Enable Invalid

Operation exceptions by setting the IOE bit, FPSCR[8].

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ARM ARM926EJ-S Specifications Page 280