ARM ARM926EJ-S Specifications download pdf (Page 42)

System Controller and Configuration Logic

2.1 About the System Controller

The System Controller in the ARM926EJ-S Development Chip is used to provide an

interface to control the operation of the chip.

The PrimeXsys System Controller supports the following functionality:

• a system mode control state machine

• crystal and PLL control

• definition of system response to interrupts

• reset status capture and soft reset generation

• Watchdog and Timer module clock enable generation

• remap control

• general-purpose peripheral control registers

• system/peripheral clock control and status.

The PrimeCell version used is SP810 SYSCTRL r0p0-00ltd0. The base address for the

System Controller registers is

0x101E0000

. For more details on the controller, see the

ARM PrimeCell System Controller (SP810) Technical Reference Manual.

2.1.1 Reset control

Reset control is used to:

• monitor the ResetStatus input signals and make them accessible to software

through the reset status register

• request a soft reset to be generated by asserting the SOFTRESREQ output for a

single SCLK cycle when any value is written to the reset status register.

Note

SCLK has the same frequency as HCLK.

SCLK, however, is present even in SLEEP mode when other clocks have been

turned off.

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ARM ARM926EJ-S Specifications Page 42